Multi-level semiconductor memory architecture and method of...

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

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Details

C365S230030, C365S072000, C365S051000

Reexamination Certificate

active

07020001

ABSTRACT:
An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.

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