Multi-level round robin arbitration system

Details Multi-level round robin arbitration system Multi-level round robin arbitration system

1996-12-24

1998-03-17

Harvey, Jack B.

395287, 395727, 395731, G06F 1314, G06F 1337

Patent

active

057297029

ABSTRACT:
Arbitration means for arbitrating between computer devices A to F which compete for access to a common bus. The system provides cascaded round-robin units. Unit RR1 has ports A, B, C, and X in sequence, with port X coupled to round-robin unit RR2, which has ports D, E, F in sequence. On each cycling of unit RR1 past C to A, unit RR2 is checked and the next one of devices D to F (in the sequence determined by unit RR2) has the opportunity of bus access. A gating circuit 13 can further restrict bus accessing by unit RR2's devices, by timing or counter control. A third round-robin unit can be added coupled to unit RR1 (which would have ports A, B, C, X,Y) or to unit RR2 (which would have ports D, E, F, Y). The assignment of devices to ports can be controllable by a matrix switch and device assignment memory.

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patent: 5303382 (1994-04-01), Buch et al.
patent: 5430848 (1995-07-01), Waggener

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