Multi-level memory for verifying programming results

Details Multi-level memory for verifying programming results Multi-level memory for verifying programming results

1998-01-29

2000-02-22

Mai, Son

Static information storage and retrieval

Floating gate

Particular biasing

36518503, 36518524, G11C 1606

Patent

active

060287926

ABSTRACT:
A multi-level memory comprises an electrically programmable memory cell having at least an erased state, a first programming state and a second programming state, and a programming circuit for programming data by repeating a programming operation for a certain program by applying a programming voltage to the memory cell, a first programming verification operation for confirming whether or not the memory cell reached the first programming state after the programming operation, or a second programming verification operation for confirming whether or not the memory cell reached the second programming state after the programming operation, wherein the programming circuits repeat the programming operation and the first programming verification operation except for the second programming operation in the first period of the data programming, and repeats the programming operation, the first programming verification operation and the second programming verification operation in the second period after the first period of the data programming.

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Young-Joon Choi et al.; "A High Speed Programming Scheme For Multi-Level NAND Flash Memory" Jun. 13, 1996; pp. 170-171.
Tae-Sung Jung et al.; "A 117-mm.sup.2 3.3-V Only 128-Mb Multilayer NAND Flash Memory For Mass Storage Applications"; IEEE Journal of Solid State Circuits;. vol. 31. No. 11, Nov. 1996; pp. 1575-1583.
European Search Report; Application No. EP 98 10 1617; Apr. 29, 1999.

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