Static information storage and retrieval – Floating gate – Multiple values
Patent
1999-05-05
2000-08-08
Nelms, David
Static information storage and retrieval
Floating gate
Multiple values
36518518, 36518523, G11C 1134
Patent
active
061011215
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
This invention relates to a multi-level type of memory circuit for binary information.
Memories of this type are usually termed "non-volatile" because of their capability to retain stored information over very long time periods, even in the absence of a power supply, and include the EPROM, EEPROM, and FLASH EEPROM families.
BACKGROUND OF THE INVENTION
Known from U.S. Pat. Nos. 5,218,569 and 5,394,362 are multi-level non-volatile memories of this type. The construction of a FLASH EEPROM multi-level memory is also described in an article TA 7.7, "A Multilevel Cell 32 Mb Flash Memory", ISSCC95 Conference, Feb. 16, 1995.
These publications also tackle the reading problem, that is the difficulty of discriminating among four different, fairly tightly packed levels for the cell threshold voltages.
From U.S. Pat. No. 4,964,079 a particular read circuit for multi-level non-volatile memories of this type is known.
All these read circuits and methods provide for the application, between the gate and source terminals of a cell being read, of a read voltage from a row decoding circuit which is powered by a supply circuit. The current flowing into the channel of the MOS transistor, or the voltage at the drain terminal, for example, is then measured and compared to currents or voltages having reference values.
This is also the case with two-level memories. Known from U.S. Pat. No. 5,291,446 is a power supply circuit for a row decoding circuit which suits the effectuation of read, write, and erase operations on two-level non-volatile memories. This power supply circuit comprises a read voltage generating section effective on request to output a voltage corresponding to the supply voltage, a write voltage generating section effective on request to output a boosted positive voltage with respect to the supply voltage, and an erase voltage generating section effective on request to output a highly negative voltage with respect to ground.
The present invention sets out from the idea of having the different threshold voltage levels for multi-level non-volatile memories sufficiently spaced apart to make the read circuit significantly less critical.
The situation is complicated, however, by the distribution of the various cell characteristics after write and/or erase operations, accurate as these may be.
SUMMARY OF THE INVENTION
The idea underlying this invention is one of having the gate-source voltage VGS thoroughly under careful control, so that current and/or voltage readings can be performed with the utmost accuracy.
This requires the availability of a read voltage generator which is unrelated to the supply voltage, can overtake it, and is preferably regulated.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be better appreciated from the following description, to be read in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates cell characteristics vs. associated levels and gain variations;
FIG. 2 illustrates the architectures of a conventional electronic storage device and one according to the invention;
FIG. 3 shows distributions of cell threshold voltages vs. associated levels; and
FIGS. 4 and 5 show first and second circuit diagrams for part of a generating circuit according to the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 depicts an ideal situation in which the cells associated with one level have exactly the same threshold voltage. In the instance of FIG. 1, there are four discrete levels DL0, DL1, DL2, DL3 provided which are associated with four discrete cell threshold voltage values L0, L1, L2, L3. This can only be obtained by adopting extremely complicated write and erase methods, and such a situation can at best be approached in actual practice.
Irrespective of the method used, the characteristics of the various cells associated with one level are bound to be different because the manufacture of integrated circuits cannot yield perfectly identical cells. Thus, such characteristics will show a distribution, as indicated by dash line
REFERENCES:
patent: 5218569 (1993-06-01), Banks
patent: 5511026 (1996-04-01), Cleveland et al.
Galanthay Theodore E.
Ho Hoai V.
Nelms David
STMicroelectronics S.r.l.
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