Multi-level memory cell sensing

Details Multi-level memory cell sensing Multi-level memory cell sensing

2006-12-14

2009-11-24

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Floating gate

Multiple values

C365S185130, C365S185210, C365S189090

Reexamination Certificate

active

07623373

ABSTRACT:
The delay arising from wordline capacitance in multi-level memories may be reduced by adding switched transistors along the wordline path. Also, the wordline may be pre-charged to a high level and then the first wordline voltage level for reading may be a center level. The switched transistors may be p-devices whose n-wells are biased by a stable DC voltage. Nodes along the wordline may float when not accessed. Finally, a distributed voltage generator may be used.

REFERENCES:
patent: 5265052 (1993-11-01), D'Arrigo et al.
patent: 5687352 (1997-11-01), Beat
patent: 5889698 (1999-03-01), Miwa et al.
patent: 6801452 (2004-10-01), Miwa et al.
patent: 2006/0028898 (2006-02-01), Sibigtroth et al.
patent: 2006/0221758 (2006-10-01), Petti et al.
patent: 2007/0008780 (2007-01-01), Jung et al.
patent: 2007/0047300 (2007-03-01), Lee et al.
patent: 2007/0070745 (2007-03-01), Versen et al.
patent: 2007/0171708 (2007-07-01), Tedrow et al.
Tedrow et al., “Multi-Level Memory Cell Sensing”, U.S. Appl. No. 11/320,529, filed Dec. 28, 2005.

Affiliated with

Also associated with

Rating

Multi-level memory cell sensing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-level memory cell sensing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-level memory cell sensing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4127571