Multi-level memory cell programming methods

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S185180, C365S185240, C365S189090, C365S210120

Reexamination Certificate

active

07639533

ABSTRACT:
A method for programming a plurality of multi-level memory cells described herein includes iteratively changing a bias voltage applied to a first memory cell to program the first memory cell to a first threshold state and detecting when the first cell reaches a predetermined threshold voltage. The bias voltage applied to the first memory cell upon reaching the predetermined threshold voltage is recorded. A second memory cell is programmed to a second threshold state by applying an initial bias voltage to the second memory cell which is function of the recorded bias voltage.

REFERENCES:
patent: 5999445 (1999-12-01), Rolandi et al.
patent: 6714457 (2004-03-01), Hsu et al.
patent: 6847550 (2005-01-01), Park
patent: 6870763 (2005-03-01), Banks
patent: 7110300 (2006-09-01), Visconti et al.
patent: 7180780 (2007-02-01), Ho et al.
patent: 2007/0262388 (2007-11-01), Ho et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Multi-level memory cell programming methods does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-level memory cell programming methods, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-level memory cell programming methods will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4106621

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.