Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
1999-01-14
2001-04-10
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185200, C365S189090
Reexamination Certificate
active
06215697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory cell devices, and more particularly to a non-volatile memory cell device and method which provides for improved self-converged programming of multiple bit levels.
2. Description of Related Art
Non-volatile memory cells are used to store bits of information which comprise digital words and the like. Such memory cells include floating gate transistor devices which have a drain, source, and gate nodes. The gate includes a control gate for application of a voltage, and a floating gate which floats in a layer of material between the device substrate and control gate. Voltages are applied across the nodes in such a way as to induce current flow through the device and cause hot electrons to jump over to the floating gate. The bits of information are therefore stored as a charge or voltage level on the floating gate of the cell, and the charge will remain until the cell is erased or reprogrammed. In the past, memory cells have commonly been used to store two levels of information, e.g. high for “1” or “on,” and low for “0” or “off.” These on and off states are arranged in collected memory cells to comprise binary strings of information which are used by computers and digital processing devices.
Memory cells have also been used to store multiple levels of data on an individual cell. Instead of two states (on or off), a series of levels can be programmed into the memory cell and then read back as multiple states. For instance three levels will provide four data bits for a single cell (e.g. zero plus three distinct voltage levels). Accordingly, this will provide higher storage densities for a given number (or array) of memory cells. Multi-level programming of devices such as flash EEPROMs (electronically erasable programmable read only memories) will allow for increased storage capacity without increasing the die size used to form the overall device. The end result is a reduced cost per bit.
For realizing multi-level programming, accurate control of the amount of charge placed on the floating gate of a memory cell is important. Many different programming methods have been previously proposed to control the amount of charged stored on the floating gate, such as program-and-verify and self-convergence methods. The program-and-verify method is widely used and involves programming the memory cell in a ramped or step-wise fashion via a programming pulse. After each programming step is applied, a verification step is performed to confirm whether the desired level on the memory cell has been achieved. Problems inherent with this method include slow programming speed, as each programming and verification step takes a certain amount of time to perform. In addition, a very stable pulse control is necessary to prevent overshoot of each programming level. Examples of modern program-and-verify methods include: M. Bauer et al., “A Multilevel-Cell 32 Mb Flash Memory,” IEEE ISSCC Digest of Technical Papers, pp. 132-133, 1995; and Y. Choi et al., “A High Speed Programming Scheme For Multi-Level NAND Flash Memory,” Symp. on VLSI Circuits Digest of Technical Papers, pp. 170-171, 1996.
Accordingly, self-convergence methods provide advantages regarding programming speed and pulse control requirements. In general, the memory cell is programmed by connecting the drain node to a dataline, the gate node to certain voltage, and the source node to a current source or ground (hence the line is also referred to as a source line). Note also that drain side sensing configurations can also be used. When a memory cell is programmed to a higher target threshold voltage (Vt), the voltage at the current source (Vs) will become proportionally lower to keep relatively the same programming current through the memory cell. Thus, Vt and Vs of the memory cell have a one-to-one correlation. By monitoring Vs, the corresponding Vt can be achieved through this correlation. One method employing this effect is described in U.S. Pat. No. 5,712,815 (see
FIG. 1
in detailed description). Three reference voltages are used to define memory cells with four different levels. The current source voltage Vs is compared to the desired reference voltage Vref, and when Vs drops below Vref, then the programming will stop automatically. An array of reference memory cells is also provided which are programmable to different reference levels. It has been found that for read operations, a voltage margin is needed above the target voltage level to compensate for possible drops that might occur as a result of the read. The differently programmed reference cells provide this read margin.
Improved memory cell devices and programming methods are required, however, to achieve a tighter distribution of read current and programming levels in light of such detrimental things including loading effects, process variations, temperature variations, and supply voltage variations. A tighter distribution will provide the benefit of even more levels being made available for multiple bits from a single cell.
SUMMARY OF THE INVENTION
The present invention provides an improved memory cell device and method for self-converged programming of a multi-levels on an individual memory cell. As a memory cell is programmed upwards to a target voltage level, the voltage across a current source (Vs) coupled to the source node (or source line) will decrease proportionally in order to keep the programming current through the cell the same. Hence by tracking the Vs associated with the memory cell, a target threshold voltage (Vt) level can be achieved via programming. A reference cell, which can easily be configured to be non-programmable dummy cell, is also associated with the memory cell and shares the same wordline and dataline voltages during programming. The threshold voltages of the dummy cells are controlled by voltages coming from a stable voltage regulator. When the reference cell is configured to be non-programmable, then the Vs of the dummy cell is fixed during programming. By comparing the Vs of the memory cell and the dummy cell, the converged threshold voltage of the memory cell will be the same as the threshold voltage of the dummy cell if their gate coupling ratios (GCRs) are equal. The term GCR applies to a floating gate cell and is the ratio of charge which ends up on the floating gate from a charge applied to the control gate due to coupling effects between the two gates. A GCR and threshold voltage (Vt) controller is provided between the memory cell and the dummy cell in order to adjust the threshold voltage apparent on the dummy cell, and hence the Vs coming from the dummy cell. By comparing the Vs of the memory cell to a reference voltage which represents the Vs of a dummy cell (instead of a constant voltage as proposed by the prior art), a tighter distribution of read current can be obtained.
While individual cells have been discussed for representative purposes, in practice the memory cells and dummy cells will exist as part of respective arrays of cells arranged in rows and columns. Each memory cell and respective dummy cell will share a common wordline and be coupled to corresponding datalines. The memory cell to be programmed (and the corresponding dummy cell) are selected via a wordline decoder (for the row) and the datalines, or bitlines (for the column). The result of the comparison of the current source voltages will be used to drive a program controller and stop programming if the memory cell voltage level has converged to a target level, which has generally been set to be the threshold voltage of the dummy cell.
Therefore according to one aspect of the present invention, a memory cell device and programming method are provided wherein the current source voltage (Vs
1
) of a memory cell is compared with the current source voltage (Vs
2
) of an associated non-programmable dummy cell having a threshold voltage set to a target voltage for the memory cell. When current source voltages are approximately equal, the memory cell voltage level has converged to the targe
Chen Shi Xian
Lu Tao Cheng
Shyu Der Shin
Tsai Wen Jer
Wang Mam Tsung
Haynes Mark A.
Haynes & Beffel LLP
Le Thong
Macronix International Co. Ltd.
Nelms David
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