Multi level mask ROM with single current path

Details Multi level mask ROM with single current path Multi level mask ROM with single current path

1999-03-04

2001-07-31

Munson, Gene M. (Department: 2811)

Static information storage and retrieval

Read only systems

Semiconductive

C257S391000

Reexamination Certificate

active

06269017

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to the field of microelectronic read-only memory (ROM). More particularly, the invention relates to the field of multilevel Mask ROM.
2. Discussion of the Related Art
Conventional Mask ROMs have recently been multilevel programmed. Multilevel programming permits more data to be stored per memory cell by defining more than two (e.g., 4) memory cell states. Each of these states is defined by a different voltage threshold, which is a function of the amount of dopant implanted into the channel of a given memory cell during mask programming. The difference in multi-level thresholds may be less than one volt. Such a sub-volt difference in multi-level thresholds can be necessitated by the operating voltage of the Mask ROM (e.g., 3 V).
A problem with this technology has been that the sub-volt threshold difference tends to cause read errors. The narrow difference between voltage thresholds requires a sensitive system that is, in-turn, sensitive to even small current leakages. Current leakage can cause the associated sense amplifier to report an incorrect value for the data being read from a memory cell of interest. Therefore, what is required is a solution that reduces multi-level Mask ROM read errors by controlling current leakage.
SUMMARY OF THE INVENTION
A primary object of the invention is to provide fixed code implantation for isolating blocks of memory cells, thereby defining a single current path during a memory cell read operation. Fixed code isolation consumes only a small area and provides good topography.
An optional object of the invention is to provide a Mask ROM that uses the same select transistors for two banks of memory cells, thereby reducing select transistor overhead. Another optional object of the invention is to provide a Mask ROM having only one sense amplifier per block, thereby reducing sense amplifier overhead. Another optional object of the invention is to provide a Mask ROM having odd and even word line decoders, thereby dividing the memory cell array into a plurality of banks.
A first aspect of the invention is implemented in an embodiment that is based on a Mask ROM comprising: an array of memory cells including a first bank of memory cells and a second bank of memory cells, and the first bank of memory cells separated from the second bank of memory cell by a set of select lines, wherein the first bank of memory cells and the second bank of memory cells includes at least one fixed code implanted memory cell column. A second aspect of the invention is implemented in an embodiment that is based on a method of reading data from a Mask ROM memory cell comprising: utilizing the Mask ROM. A third aspect of the invention is implemented in an embodiment that is based on an integrated circuit that includes the Mask ROM.
These, and other, objects and aspects of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating preferred embodiments of the invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the invention without departing from the spirit thereof, and the invention includes all such modifications.


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