Multi-level flash memory with temperature compensation

Details Multi-level flash memory with temperature compensation Multi-level flash memory with temperature compensation

2005-03-22

2005-03-22

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185200, C365S185210, C365S185220

Reexamination Certificate

active

06870766

ABSTRACT:
A multi-level semiconductor memory device preferably includes a plurality of wordlines connected to memory cells configured to store multi-level data. A first circuit supplies a temperature-responsive voltage to a selected wordline in order to read a state of a selected memory cell. A second circuit supplies a predetermined voltage to non-selected wordlines. The first circuit preferably includes a semiconductor element that varies its resistance in accordance with temperature. Reliable program-verifying and reading functions are preferably provided despite migration of threshold voltage distribution profiles due to temperature variations.

REFERENCES:
patent: 5864504 (1999-01-01), Tanzawa et al.
patent: 6349060 (2002-02-01), Ogura
patent: 6667904 (2003-12-01), Takeuchi et al.

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