Multi level flash memory device and program method

Details Multi level flash memory device and program method Multi level flash memory device and program method

2006-05-30

2006-05-30

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189011, C365S185280

Reexamination Certificate

active

07054199

ABSTRACT:
We describe a multi level flash memory device and program method. The multi level flash memory device includes a plurality of memory cells, each storing an amount of charge indicative of more than two possible states and control circuitry coupled to the memory cells. The control circuitry to applying a programming voltage alternating with a verification voltage to the memory cells until all are at a desired state and applying at least one additional programming voltage to the cells in a highest state without applying a verification voltage. The method includes applying at least one programming pulse to the cells, verifying that each cell has reached the desired state, selecting the cells that are programmed for a highest state, and applying at least one additional programming pulse to the selected cells without further verifying their state.

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Ken Takeuchi, et al. “A Multipage Cell Architecture For High-Speed Programming Multilevel NAND Flash Memories”, IEEE Journal of Solid-State Circuit, vol. 33, No. 8, Aug. 1998. pp. 1228-1238.

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