Multi-level encoding system

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340347DD, 325 38A, G06F 1300, G06F 300

Patent

active

041187911

ABSTRACT:
An encoder providing on a single terminal of a circuit package a composite serial data stream containing both stored data bits of a multistage binary memory and a clock signal needed for decoding the data. A parallel to serial converter serially shifts the stored binary data bits to an output thereof in response to clock pulses of an internal clock, and a logic circuit responsive to both the internal clock and the serial binary data from the converter generates first, second and third signals of amplitudes discernibly different from one another respectively in response to 1-state data bits, 0-state data bits and the termination of clock pulses. Two fixed inputs to the converter respectively provide a 1-state start bit at the beginning of the set of data bits and a 0-state stop bit at the end of the set of data bits for purposes of decoding. An amplitude discriminating decoder uses the periodic third signals and the start and stop bits to decode the serial data.

REFERENCES:
patent: 3587088 (1971-06-01), Franaszek
patent: 3678194 (1972-07-01), Orrell, Jr.
patent: 3753113 (1973-08-01), Maruta
patent: 3754237 (1973-08-01), DE Meux
patent: 3927401 (1975-12-01), McIntosh
patent: 3952298 (1976-04-01), Winkelmann
patent: 3988676 (1976-10-01), Whang
patent: 4003041 (1977-01-01), VAN Duren
patent: 4020282 (1977-04-01), Halpern
patent: 4056828 (1977-11-01), Furuta

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