Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2002-06-03
2003-11-04
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S154000
Reexamination Certificate
active
06642873
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates generally to oversampling analog-to-digital (A/D) converters, and particularly to multi-bit sigma-delta A/D converters with reduced element mismatch and circuit complexity.
Sigma-delta A/D converter is an oversampling A/D converter, also referred to as sigma-delta modulator, delta-sigma A/D converter, and delta-sigma modulator. The sigma-delta A/D converter has been successfully applied in communications and other signal processing areas. Conventional sigma-delta A/D converters rely on large oversampling ratio and 1-bit quantizer to ensure linearity and simple circuit implementation, as described in J. C. Candy and G. C. Temes: “Oversampling delta-sigma data converters”, IEEE Press, New York 1992.
Compared to the 1-bit sigma-delta A/D converter, a multi-bit sigma-delta A/D converter is more stable and provides large dynamic range and high resolution without increasing the oversampling ratio.
FIG. 1
illustrates the basic principle of the multi-bit sigma-delta A/D converter. An analog input signal is fed into the converter through the first input terminal of summer
101
. The output of the summer is coupled to loop filter
102
, which is either one or more low-pass filters so-called integrators for low-pass or baseband applications, or one or more band-pass filters for bandpass applications. The loop filter
102
can be continuous time or discrete-time filters. The output of the loop filter
102
is still analog (continuous or discrete-time) signal and it is coupled to N-level quantizer
103
. The N-level quantizer
103
is a flash-type analog-to-digital converter and converts analog signal into digital thermometer code. A thermometer code is a code where all of the bits are equally weighted. For example, a 4-bit binary code converted to a thermometer code would require 15 equally weighted bits (the “all bits off” state does not require an out bit). If the input number was “8”, then the thermometer code would have the bottom 8 bits set to “1” and the top 7 bits set to “0” (An inverted form, where the bottom bits are set to “0” and the top bits are set to “1” may also be referred to as a thermometer code). The digital output of the quantizer
103
is fed back through N-level digital-to-analog (D/A) converter
104
to the second input terminal of the summer
101
negatively, and that completes the feedback loop, the core of the sigma-delta A/D converter. The digital output of the quantizer
103
, in the form of thermometer code, is also coupled to encoder
105
, which transforms the thermometer code into binary. The output of the encoder
105
is coupled to decimator
106
, which filters out noise and finally outputs a data word of high resolution at a rate much lower than the oversampling rate.
However, a drawback associated with the multi-bit sigma-delta A/D converter is nonlinear effect called element mismatch, which is primarily caused by the N-level D/A converter in the feedback path of the multi-bit sigma-delta A/D converter. In the N-level D/A converter, a plurality of elements such as capacitors, resistors, current sources, and the like, are configured in such a way that a selected number of the elements release their electrical energy into a summing junction that produces an analog output signal equivalent to the digital input.
FIG. 2
illustrates the basic principle of the N-level D/A converter incorporated with first stage integrator of a sigma-delta A/D converter, where a 5-level switched-capacitor D/A converter is illustrated as an example. Five switches,
21
,
22
,
23
,
24
, and
25
, are controlled by feedback digital thermometer code; the switches' on or off actions charge or discharge five correspondent capacitors labelled as C
1
, C
2
, C
3
, C
4
, and C
5
. The energy in the five capacitors is then summed at a feedback capacitor labelled as C through the simple summing circuit comprising op-amp
28
. The analog output of the op-amp
28
represents the digital control signal. Variation inevitably exists among the elements due to manufacturing variation, temperature, aging, etc. Although the absolute error from one element to another can be tightly controlled, the cumulative effect of the mismatched elements can cause significant nonlinear distortion. The element mismatch problem does not arise in 1-bit case because perfect linearity is guaranteed by virtue of the fact that only a single element is used to convert the digital signal to analog.
There are some known techniques of tackling the element mismatch problem in the multi-bit sigma-delta A/D conversion. For example, precise laser trimming technique can reduce the element mismatch but is of high cost; calibration and recalibration techniques work but need additional circuit and processing power.
FIG. 3
illustrates another known technique of digitally correcting the error at the output of encoder
105
by introducing digital correction unit
301
between the encoder
105
and the decimator
106
. The digital correction unit
301
may use a RAM-based LUT (look up table) to convert the nonlinearly distorted output readings into correct output data words.
Another known technique of tackling the D/A converter element mismatch is dynamic element matching, in which the D/A converter elements are randomly selected. The Random selection of the elements spreads the nonlinear error across the spectrum, making it like white noise, as described by R. Carely, “A noise-shaping coder topology for 15+bit converter,” IEEE Journal of Solid-State Circuits, pp. 267-273, Apr. 1989.
FIG. 4
illustrates that a random selection functional block
401
is inserted between the N-level D/A converter
104
and the output of the N-level quantizer
103
. A particular dynamic element matching technique is called data weighted averaging (DWA) method that can shape the noise introduced by the DAC element mismatch, as described by R. T. Baird and T. S. Fiez, “Linearity enhancement of multi-bit sigma-delta A/D and D/A converters using data weighted averaging,” IEEE Transactions of Circuits and Systems II, pp. 753-762, Dec. 1995.
More recently, some particular implementations of the dynamic element matching technique have been proposed. See, for example, Chen et al., U.S. Pat. No. 6,304,608, issued Oct. 16, 2001 and entitled “Multi-bit Sigma-delta Converters Employing Dynamic Element Matching With Reduced Baseband Tones”; and Friend et al., U.S. Pat. No. 6,218,977, issued Apr. 17, 2001 and entitled “Methods and Apparatus for Distributing Mismatched Error Associated with Data Converter Elements”.
It is noted that the known techniques of tackling the element mismatch in the multi-bit sigma-delta A/D converter are either of high cost and/or add circuit complexity.
It is therefore an object of the present invention to provide a novel multi-level D/A converter that is incorporated with a multi-level quantizer in the multi-bit sigma-delta A/D converter, so that it actually reduces both the circuit complexity and the element mismatch significantly.
BRIEF SUMMARY OF THE INVENTION
In the present invention, a multi-level digital-to-analog (D/A) converter is incorporated with a multi-level quantizer in a milti-bit sigma-delta analog-to-digital (A/D) converter. The multi-level D/A converter is realized by feeding back reference voltages of the multi-level quantizer through a switch, which is controlled by the output of the quantizer through a logic unit. Summation of electrical energy from D/A converter elements, which is found in conventional D/A converters, is avoided so that the element mismatch and circuit complexity of the sigma-delta AID converter are reduced significantly. The multi-level D/A converter incorporated with the multi-level quantizer according to the present invention comprises: N comparators, a switch having single pole and N throws, a voltage divider network of dividing a voltage reference signal into various voltage levels that are applied to the N comparators and to the switch, and a switching control logic unit of controlling the switch.
A multi-bit sigma-delta A/D co
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