Multi-level conductor process in VLSI fabrication utilizing an a

Details Multi-level conductor process in VLSI fabrication utilizing an a Multi-level conductor process in VLSI fabrication utilizing an a

1994-07-15

1995-05-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437927, 148DIG73, H01L 2144

Patent

active

054139627

ABSTRACT:
This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used in forming the structure is etched away leaving an air dielectric between the levels. The electrode metal and the inter-level metal studs are coated with a thin envelope oxide and the entire structure is covered with a passivation layer using material with a poor step coverage. The structure of this invention provides reduced parasitic capacitance, better step coverage in interconnecting layers, and improved circuit performance.

REFERENCES:
patent: 4169000 (1979-09-01), Riseman
patent: 4710794 (1987-12-01), Koshino et al.
patent: 4754316 (1988-06-01), Reid
patent: 5000818 (1991-03-01), Thomas et al.
patent: 5216537 (1993-06-01), Hornbeck
patent: 5227658 (1993-07-01), Beyer et al.
patent: 5310700 (1994-05-01), Lien et al.
patent: 5324683 (1994-06-01), Fitch et al.

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