Multi-level conductive structure including low capacitance mater

Details Multi-level conductive structure including low capacitance mater Multi-level conductive structure including low capacitance mater

1997-09-29

1999-11-02

Kelley, Nathan K.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257758, 257635, H01L 2348

Patent

active

059776358

ABSTRACT:
A method for forming a multi-level conductive structure on an integrated circuit. The method includes forming a first conductive layer 108 and forming a first dielectric layer 112 above the first conductive layer. The method further includes forming a second conductive layer 302 above the first dielectric layer. There is also included etching through the second conductive layer and at least partially into the first dielectric layer to form a trench 706 in the second conductive layer and the first dielectric layer, thereby removing at least a portion of the dielectric layer and forming a first conductive line 503 and a second conductive line 505 in the second conductive layer. Further, the method includes depositing a low capacitance material 908 into the trench. The low capacitance material represents a material having a dielectric constant lower than a dielectric constant of the first dielectric layer.

REFERENCES:
patent: 5310700 (1994-05-01), Lien et al.
patent: 5548159 (1996-08-01), Jeng
patent: 5691573 (1997-11-01), Avanzino et al.
patent: 5789818 (1998-08-01), Havemann
patent: 5847464 (1998-12-01), Singh et al.

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