Multi-level conduction structure for VLSI circuits

Details Multi-level conduction structure for VLSI circuits Multi-level conduction structure for VLSI circuits

1996-06-27

1998-10-27

Whitehead, Carl W.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257276, 257774, 257776, 257644, 257650, H01L 23485, H01L 23535, H01L 23532, H01L 2941

Patent

active

058281215

ABSTRACT:
This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used in forming the structure is etched away leaving an air dielectric between the levels. The electrode metal and the inter-level metal studs are coated with a thin envelope oxide and the entire structure is covered with a passivation layer using material with a poor step coverage. The structure of this invention provides reduced parasitic capacitance, better step coverage in interconnecting layers, and improved circuit performance.

REFERENCES:
patent: 3844831 (1974-10-01), Cass et al.
patent: 4169000 (1979-09-01), Riseman
patent: 4404733 (1983-09-01), Sasaki
patent: 4710794 (1987-12-01), Koshino et al.
patent: 4807016 (1989-02-01), Douglas
patent: 5000818 (1991-03-01), Thomas et al.
patent: 5216537 (1993-06-01), Hornbeck
patent: 5227658 (1993-07-01), Beyer et al.
patent: 5391517 (1995-02-01), Gelatos et al.

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