Multi-level charge-coupled device memory system including analog

Details Multi-level charge-coupled device memory system including analog Multi-level charge-coupled device memory system including analog

1979-12-31

1981-12-15

Hecker, Stuart N.

Static information storage and retrieval

Analog storage systems

365183, G11C 2700, G11C 1134

Patent

active

043063004

ABSTRACT:
A digital-to-analog conversion (DAC) circuit and trigger comparator combination is described for encoding and decoding charge packets in a common-well multi-level signal charge-coupled memory device (CCD). The DAC circuit, which may be of the weighted capacitor type, is used to generate a staircase waveform and to create the common-well under a first gate in the CCD. The trigger comparator adjacent to a second gate in the CCD is a detection circuit which stays in one binary state until an input charge signal is received, whereupon it switches state. In particular, the weighted capacitor DAC contains an extra offset bit which is used in the analog-to-digital or regeneration operation such that when the trigger comparator switches state, the digital input to the DAC at that time correctly represents the signal charge being converted. In one embodiment a circular serial-parallel-serial memory structure is employed as the multi-level CCD memory system.

REFERENCES:
patent: 4077035 (1978-02-01), Yee
patent: 4130894 (1978-12-01), Merrill et al.
patent: 4135104 (1979-01-01), Allen
patent: 4165537 (1979-08-01), Engeler et al.
patent: 4202046 (1980-05-01), Ward
Jaeger, "Improved Throughput for CCD Multilevel Stoage", IBM Tech. Disc. Bul., vol. 20, No. 2, 7/77, pp. 789-790.

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