Multi-level cell memory structures with enlarged second bit...

Details Multi-level cell memory structures with enlarged second bit... Multi-level cell memory structures with enlarged second bit...

2006-12-21

2008-12-30

Mai, Son L (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030, C365S185180

Reexamination Certificate

active

07471568

ABSTRACT:
Multi-level cell memory devices comprise a charge trapping structure with an enlarged second bit operation window formed by hole injection through a gate electrode or substrate for producing multiple logic levels on each storage side of the charge trapping structure. A hole injection process is conducted through either a gate electrode or substrate to cause fringe-induced effect. Hole charges are stored in a charge trapping layer that intersects with a word line and the hole charges are stored along fringes of the word line. Each memory cell in the MLC memory device includes a total of 2 m bits with m bits for each side of the memory cell, a total of 2*2mmultiple voltage threshold Vt distributions with 2mmultiple voltage threshold Vt distributions for each side of the memory cell, and a total of 2*2mlogic states with 2mlogic states for each side of the memory cell.

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