Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Patent
1995-04-03
1996-10-15
Carroll, J.
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
H01L 2900
Patent
active
055657036
ABSTRACT:
A multilevel antifuse structure characterized by a substrate, a first antifuse structure formed above the substrate, and a second antifuse structure formed above the first antifuse structure. The first antifuse structure preferably includes a first conductive layer, a first antifuse layer disposed over the first conductive layer, a first dielectric layer disposed over the first antifuse layer and provided with a first via hole, and a first conductive via formed within the first via hole. The second antifuse structure preferably includes a second conductive layer, a second antifuse layer disposed over the second conductive layer, a second dielectric layer disposed over the second antifuse layer and provided with a second via hole, and a second conductive via formed within the second via hole. Preferably, the first antifuse layer and the second antifuse layer are patterned into a plurality of antifuse regions which are either vertically aligned or vertically staggered with respect to each other. A method for making a multilevel antifuse structure in accordance with the present invention includes the steps of forming a first antifuse structure over a substrate, and forming a second antifuse structure over the first antifuse structure. In one embodiment, the first antifuse structure and the second antifuse structure are vertically aligned, and are interconnected in parallel. The parallel interconnection is preferably accomplished by tungsten vias formed by either a blanket tungsten deposition and subsequent etch-back, or by a selective tungsten deposition.
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Patent Abstracts of Japan, vol. 6, No. 211 (E-137); Publication No: JP57117255; Publication Date: 21-07-82; Application No: JP810002974; Application Date: 12-01-81; Inventor: H. Yutaka.
An FPGA Family Optmized for High Densities and Reduced Routing Delay, Ahrens et al., IEEE 1990 Custom Integrated Circuits Conference, (1990) pp. 31.5.1-31.5.4.
Carroll J.
VLSI Technology Inc.
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