Multi-layered, integrated circuit package having reduced parasit

Details Multi-layered, integrated circuit package having reduced parasit Multi-layered, integrated circuit package having reduced parasit

1995-10-30

1997-06-24

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257700, 257697, H01L 2348

Patent

active

056419880

ABSTRACT:
A multi-layered, high performance integrated circuit package is disclosed having a number of design features which increase the performance and manufacturability of the integrated circuit package, and reduce the effects of parasitic noise generated within the package. The metallic layers connecting contact fingers formed on ledges around the periphery of a die cavity area, to their respective package pins are organized such that a ground metallic layer is interposed between each pair of input/output signal metallic layers, and each input/output signal metallic layer is sandwiched between a pair of metallic layers wherein one layer of the pair is connected to a voltage supply and the other layer of the pair is connected to a corresponding ground reference. On one of the ledges, contact fingers corresponding to a first set of input/output signals are evenly dispersed around contact fingers corresponding to the ground reference, and on another one of the ledges, contact fingers corresponding to a second set of input/output signals are evenly dispersed around contact fingers corresponding to the voltage supply. On a bottom surface of the integrated circuit package a plurality of pins are arranged in a pin-grid-array, and pins corresponding to the voltage supply and ground reference are placed in the four outer corners of the bottom surface, so as to minimize parasitic noise generated on the voltage and ground lines connected to these pins, by active circuitry of the packaged integrated circuit.

REFERENCES:
patent: 5173767 (1992-12-01), Lange et al.
patent: 5220489 (1993-06-01), Barreto et al.

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