Multi-layered contacting for securing integrated circuits

Details Multi-layered contacting for securing integrated circuits Multi-layered contacting for securing integrated circuits

1995-12-20

1998-10-20

Tsai, Jey

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Rendering selected devices operable or inoperable

438455, H01L 2182

Patent

active

058245715

ABSTRACT:
A method for securing confidential circuitry from observation by unauthorized inspection, and a secure circuit immune from unauthorized inspection according to the method. In one embodiment, confidential data or circuitry is placed on a face of separate silicon layers, each silicon layer having part of a circuit. Neither silicon layer is intelligible without the other, yet neither can be observed without destroying the other. The two silicon layers are juxtaposed, the face of the first silicon layer flush against and fused to the face of the second silicon layer, the confidential circuits on each silicon layer connecting directly with circuits on the other silicon layer without external connectors. Data stored on each face is erased or destroyed when the silicon layers are separated or one of the silicon layers is destroyed. Violence to either silicon layer of silicon, or exposure of either silicon layer of silicon to light, destroys the data or circuitry on at least one silicon layer of silicon, making the data or circuitry unreadable.

REFERENCES:
patent: 3725671 (1973-04-01), Keister et al.
patent: 4612083 (1986-09-01), Yasumoto et al.
patent: 4933898 (1990-06-01), Gilberg et al.
patent: 4956749 (1990-09-01), Chang
patent: 5644638 (1997-07-01), Thiriet

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