Multi-layer wiring substrate and manufacturing method thereof

Details Multi-layer wiring substrate and manufacturing method thereof Multi-layer wiring substrate and manufacturing method thereof

2000-02-10

2003-01-14

Cuneo, Kamand (Department: 2827)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C361S792000, C174S260000, C174S262000

Reexamination Certificate

active

06506982

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a multi-layer wiring substrate, which has a build-up laminated body configured by repeatedly laminating insulating layers and wiring layers alternately on a carrier substrate, and a method for manufacturing the substrate, and, in particular, to a multi-layer wiring substrate, which has a feature in the configuration of a carrier substrate for realizing higher density, and a method for manufacturing the substrate.
Miniaturization of electronic equipments is rapidly promoted, and a technical outlook has been presented, in which the thin film technology is made use of to realize 0.25 mm pitch with respect to packaging of semiconductors, as described in “Nikkei Micro Device” (August 1998, pp. 66 to 71).
A wiring substrate to be incorporated into such package includes a known multi-layer wiring substrate having a build-up laminated body. Such multi-layer wiring substrate having a build-up laminated body is herein referred to as a build-up substrate.
In basic technology for build-up substrates is, as disclosed in, for example, Japanese Patent No. 2739726 (Japanese Patent Unexamined Publication No.4-148590), high density packaging is realized by using the fine processing technique of a build-up layer, in which insulating layers and wiring layers are stacked one by one alternately on front and back surfaces of a printed wiring board.
However, at the stage when such technique presented itself, a core wiring substrate (to be a carrier substrate) and front and rear build-up layers are connected by forming holes by means of drilling and applying plating to such holes, which gives rise to such problems that density of the entire substrate is limited by accuracy of the drilling, and the holes restricts a wiring area.
Among those problems, restriction on the wiring area is solved by the development of that technique, in which through holes are formed in a printed substrate (that is, a carrier substrate and also called a core substrate) being a core, the through holes are filled with a resin, and then the build-up technique is applied. A structure of a semiconductor device, in which a semiconductor chip (LSI) is mounted on a multi-layer wiring substrate obtained by the build-up technique, is shown in FIG.
1
.
As shown in
FIG. 1
, a pitch “b” of through holes
12
in a core substrate
10
, formed by drilling is normally larger than a pitch “a” of terminals (solder connection)
2
on an LSI indicated by the reference numeral
1
. Therefore, when wiring layers
16
on the core substrate
10
are to be connected to wiring layers
13
on a build-up layer
11
, wiring from the LSI terminals
2
to the through holes
12
in the core substrate
10
is necessarily formed by using wiring layers
13
in the build-up layer
11
, in which insulation layers
15
and the wiring layers
13
are stacked alternately, build-up layer vias
14
, and lands
16
a
about opening portions of the through holes
12
, and thus direct connection between the LSI terminals
2
and the through holes
12
has in no way been taken into consideration.
The problem of restriction on density due to drilling has been successfully solved by the advent of the so-called coreless technique, in which the use of a printed board for a core is abandoned, and wiring sheets having fine front-to-back conductive passages formed with the laser processing and the like are stacked one another.
However, in addition to the problem such as handling required for suppressing deformation of sheets, such coreless structure offers a problem in losing an advantage of the conventional build-up technique capable of advancing most processing steps simultaneously on front and back parts.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to solve the problems of the abovedescribed conventional build-up substrate, and to provide a multi-layer wiring substrate, which realizes a carrier substrate enabled to be formed with through holes in high density, and applies the conventional build-up technique to the carrier substrate to form build-up layers thereon for high density packaging, and a manufacturing method thereof.
Therefore, to attain the above-described purposes, the inventors of the present application have investigated the functions of through holes on a core substrate in a conventional build-up substrate shown in FIG.
1
. As a result, one of the functions is the provision of electric connection in a power source, grounding, signals and so on, etc. between build-up layers
11
, which are formed on front and back sides of the core substrate . Another function is the provision of connection to signal layers in the core substrate
10
although limited to the case where multi-layer substrates are used.
Since the core substrate
10
is normally low in wiring density as compared with that in the build-up layers
11
, only the connecting function in connection with the front and back sides of the core substrate is necessary provided that the core substrate
10
be not provided with any wiring function. Hereupon, a carrier substrate will be demanded, in which through holes are arranged in high density with a desired dimensional accuracy.
FIG. 2
shows a structural model of an ideal build-up substrate
20
having a terminal pitch “a” for a LSI, and so a pitch “b” of conductors
17
connecting front and back sides of the core substrate
20
to each other must be naturally made fine to a level of the terminal pitch “a” of the LSI (the pitch a=b). It is estimated that such pitch will be made fine to 0.25 mm around the year 2002 to 2003, and if this is not realized, rewiring from an LSI to a core conductor will be needed as in the prior art. The reference signs
1
,
2
,
11
,
13
,
13
a,
and
15
refer to the same elements shown in
FIG. 1
, and therefore need not describe herein.
However, it is not necessary for through holes to be arranged in the same pitch on the level of the carrier substrate, and the pitch of the through holes can be preferably converted to the pitch of the build-up layer or of terminals of the semiconductor package, so it sufficing that the through holes per unit area can be secured in quantity as required. In view of the above, the present invention proposes a structure, which premises that a plurality of through holes are simultaneously formed in a small area.
The inventors of the present application have performed various experiments on the basis of the above investigation result to obtain an important knowledge that can attain the object of the invention as described below in details.
More specifically, a plurality of windows are provided in a foil of copper, a measure such as the blacking treatment, Ni plating and the like is used to form an irregular surface on the copper surface, and an insulating resin layer is formed closely on the surface, so that the windows are filled with the resin. The insulating resin includes resins, such as a solder resist of epoxy resin group or polyimide, which are conventionally used as an interlayer insulating film for a multi-layer wiring structure.
With such construction, it is possible to set a coefficient of thermal expansion of the entire structure close to that of the copper foil, and so to reduce a load in the thermal process. of course, a metal foil other than copper may be used in order to obtain a line expansion coefficient other than that of copper in applications of semiconductor packages and so on. This kind of resin-coated copper foil with windows is disclosed in, for example, Japanese Patent Unexamined Publication No. 6-268381, which provides a process for laminating the copper foil but does not suggest lines, in which the copper foil is used for a carrier substrate in the build-up technique.
Then, the inventors of the present application have investigated a measure of forming a plurality of through holes in window portions of the copper-resin complex structure, which has a handling quality. While the carbon dioxide laser offers a large processing speed up to 50,000 nm, the high-frequency YAG l

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