Stock material or miscellaneous articles – Structurally defined web or sheet – Discontinuous or differential coating – impregnation or bond
Patent
1993-09-13
1995-06-20
Ryan, Patrick J.
Stock material or miscellaneous articles
Structurally defined web or sheet
Discontinuous or differential coating, impregnation or bond
428615, 428620, B32B 900
Patent
active
054259827
ABSTRACT:
A multi-layer wiring structure for a semiconductor device comprises: a first insulating interlayer formed on a semiconductor substrate on which a semiconductor element is formed; an elongated lower wiring layer extending on the first insulating interlayer and connected to the semiconductor element; a second insulating interlayer formed to cover the first insulating interlayer and the lower wiring layer; a first via hole formed through the second insulating interlayer to reach the lower wiring layer; a blocking conductive layer formed to fill the first via hole; connecting to the lower wiring layer and extending over a first area on the second insulating interlayer; a third insulating interlayer formed to cover the second insulating interlayer and the blocking conductive layer; a second via hole formed through the third insulating interlayer to reach the blocking conductive layer; and an elongated upper wiring layer filling the second via hole to connect the upper wiring layer to the blocking conductive layer with a pattern extending on the third insulating interlayer; wherein the upper wiring layer overlaps the lower wiring layer at a second area as viewed in a direction perpendicular to the substrate, with the second via hole having a cross-section larger than the second area and smaller than the first area and the blocking conductive layer being made of a material different from the material of the upper wiring layer so that the blocking conductive layer functions as an etching stopper while etching patterning of the upper wiring layer.
REFERENCES:
patent: 4020221 (1977-04-01), Kusakawa et al.
patent: 4490429 (1984-12-01), Tosaki et al.
patent: 4732801 (1988-03-01), Joshi
"Next Generation Ultra LSI Process Technique", Realize Inc., Apr. 30, 1988, pp. 238-241.
Lee Kam F.
Nippon Steel Corporation
Ryan Patrick J.
LandOfFree
Multi-layer wiring structure for semiconductor device and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-layer wiring structure for semiconductor device and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-layer wiring structure for semiconductor device and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1843252