Multi-layer wiring circuit board and method for producing...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Reexamination Certificate

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Details

C438S107000, C438S110000, C438S118000, C438S125000, C438S209000, C174S254000, C174S259000, C361S752000

Reexamination Certificate

active

06902949

ABSTRACT:
First and second metal foil layers are laminated on opposite surfaces of a first insulating layer to form a first board. Then, the first and second metal foil layers are formed into predetermined conductor patterns respectively. Then, second and third insulating layers of second and third boards formed separately from the first board are laminated on the first and second metal foil layers through first and second adhesive layers respectively. Then, a thin layer portion is removed and thick layer portions are formed into predetermined conductor patterns respectively in third and fourth metal foil layers of the second and third boards.

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patent: 2001/0010303 (2001-08-01), Caron et al.
patent: 1136758 (1995-12-01), None
patent: 0 744 884 (1996-11-01), None

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