Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
1998-06-08
2001-01-09
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S010000, C438S121000
Reexamination Certificate
active
06171888
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The invention relates to mounting a semiconductor device, or integrated circuit (IC) to a lead frame, flexible lead frame, or tape, for final packaging.
BACKGROUND OF THE INVENTION
Generally speaking, there are three distinct techniques of packaging a semiconductor device, in any case said package having leads or the like exiting the package for electrically connecting the packaged die to other components, either by mounting directly to a printed circuit board or by plugging the packaged device into a socket which, in turn is mounted to a printed circuit board. These are: (1) plastic molding; (2) ceramic packaging; and (3) flat packing.
U.S. Pat. No. 5,051,813 (Schneider, et al.), incorporated by reference herein, provides an example of a plastic-packaged semiconductor device. Present plastic packaging techniques involve molding a plastic “body” around a semiconductor die. Prior to molding, the die is attached to a lead frame having a plurality of leads ultimately exiting the package for connecting the semiconductor device to external circuits, such as via conductors on a printed circuit board. Various forms of plastic packs are known, including DIP (Dual In-line Package), PQFP (Plastic Quad Flat Pack) and PLCC (plastic leaded chip carrier). The lead frame is formed from a single thin layer (foil) of conductive material, which is punched out to form individual leads. The inner ends of the leads are usually wire bonded to the active side (components, bond pads) of the die. When handling the lead frame, prior to encapsulation, it is exceptionally important to avoid damaging the closely-spaced, delicate leads.
U.S. Pat. No. 4,972,253, incorporated by reference herein, provides an example of multi-layer ceramic packages which are laminated structures of alternate conducting and non-conducting layers, formed of thick conductive film and nonconductive ceramic, respectively. Generally, the conductive layers carry only one of signals, power or ground. This approach, particularly separating the signal plane (layer) from the ground and power planes, has distinct electrical advantages, which are well known. In this type of package, the conductive layers are screened or otherwise disposed between the nonconductive layers, and a very rigid, stable package is formed. For the signal-carrying layers, lead traces are typically screened onto an underlying ceramic layer. A die is eventually disposed into an opening in the package and connected to inner (exposed) ends of the lead traces. Generally, there is little problem in damaging the lead traces, since they are well supported by an underlying ceramic layer. Generally, vias are formed in the package to connect power and ground planes to particular leads in the signal plane.
U.S. Pat. No. 4,965,702, incorporated by reference herein, provides another example of a multi-layer package, using polymeric (e.g.) insulating layers and a copper foil (e.g.) for the conductive layers. Again, an object of such a multi-layer package is to provide for an electrical multilayer conductive package which partitions (separates) the power supply system of the package from the signal transmission system as much as practical in order to optimize the performance of both.
These two multi-layer ceramic and polymer packages are also known as “chip carriers”. Both are preferably completely formed prior to mounting the semiconductor die within an opening in the chip carrier, and in both the inner leads are well-supported. Hence, both of these chip carriers inherently avoid the problem of lead damage during handling and mounting of the die.
FIGS. 1A and 1B
show an example of tape-based flat packing. As illustrated herein, a semiconductor device assembly
10
includes an upper, segmented plastic film layer
14
(formed of segments
14
A,
14
B,
14
C and
14
D), a lower plastic film layer
16
, metallic leads
18
sandwiched between the two plastic layers
14
and
16
, a metallic (preferably copper) die attach pad
20
supported between the two plastic layers
14
and
16
, a semiconductor device
22
mounted on the die attach pad
20
and bond leads
24
connecting the semiconductor device
22
to the leads
18
. It is also known to employ conductive “bumps” on the inner ends of the leads, rather than bond wires, to connect the leads to the semiconductor die
22
, in a tape automated bonding (TAB) process. The upper and lower plastic layers are suitably formed of polyimide, and form a thin, insulating supportive structure for the leads
18
. A square, insulating ring (“body frame” or “dam”)
26
is disposed atop the leads
18
between portions
14
B and
14
C of the upper plastic film layer, outside the die area. A layer-like quantity of silicone gel
28
is disposed over the die
22
and bond wires
24
, and acts as an ionic contamination barrier for the die and as a stress relief for the leads
24
during assembly of the semiconductor device assembly, and further prevents an ultimate encapsulation epoxy
30
from contacting the semiconductor die. Evidently, the inner ends of the leads
18
are very fragile, and extreme care must be exercised when assembling the die
22
to the leads
18
. In this respect, tape mounting a semiconductor die requires a similar degree of extreme care when mounting the die to the fine-pitch conductive leads.
Further examples of mounting semiconductor devices to a tape structure are shown in U.S. Pat. Nos. 4,800,419 and 4,771,330, incorporated by reference herein.
As used herein, the term “semiconductor device” refers to a silicon chip or die containing circuitry and bond sites on one face, and the term “semiconductor device assembly” refers to the semiconductor chip and associated packaging containing the chip, including external package leads or pins for connecting the semiconductor device assembly to a socket or a circuit board, and including internal connections (such as bond wires, TAB, or the like) of the chip to inner ends of the leads.
The aforementioned patents relate to semiconductor device assemblies having a high lead count, which is “de rigueur” in modern semiconductor devices. The plastic packaging and tape mounting techniques are generally indicative of methods of mounting semiconductor devices to preformed lead frames having a plurality of extremely delicate conductors connecting to the die.
As mentioned above, there are generally two techniques for connecting a die to inner ends of lead frame conductors, namely wire bonding and tape-automated bonding (TAB). In TAB, “bumps” typically formed of gold, are located on either the die (“bumped die”) or on the inner ends of the lead fingers (“bumped tape”). See, e.g., U.S. Pat. No. 4,842,662, FIGS. 5 and 6, respectively.
U.S. Pat. No. 4,842,662, incorporated by reference herein, discloses bonding integrated circuit components directly to a TAB tape, without the intermediary of a gold bump, by use of a process employing ultrasonic energy, pressure, time, heat and relative dimensions of the TAB tape. Generally, the end of a lead is “downset” (urged down) onto a die. (See column 6, lines 5-8) This may be thought of as a “bumpless” TAB process.
While the above-referenced patents teach various techniques of forming lead frames, TAB tapes, and the like, and various techniques for connecting semiconductor dies to same, these techniques generally involve only one layer, or plane, of patterned metal conductors (lead fingers), which single conductive layer is represents a single plane carrying signals, power and ground to the semiconductor die.
As mentioned hereinabove, it is electrically desirable to provide distinct planes for carrying signal, power and ground from leads (or pins) exiting the package to the die within the package.
U.S. Pat. No. 4,933,741, incorporated by reference herein, discloses a multilayer package for integrated circuits having a ground plane (
20
) electrically isolated from a plane of conductors (
14
) by means of an insulating layer (
16
) formed of polyimide. The ground plane (
20
) is connected to selected conductors (
14
) by mea
Lynch Brian
McCormick John
Collins D. M.
LSI Logic Corp.
Picardat Kevin M.
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