Multi-layer substrate structure for reducing layout area

Details Multi-layer substrate structure for reducing layout area Multi-layer substrate structure for reducing layout area

2006-03-28

2006-03-28

Tran, Mai-Huong (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S275000, C438S017000, C438S064000, C438S067000, C438S107000, C438S110000

Reexamination Certificate

active

07019401

ABSTRACT:
The present invention provides a multi-layer substrate structure for reducing layout area, including a first core layer, a second core layer, and a set of coupled transmission line. The first core layer includes a first surface connected to a power supply layer and a second surface corresponding to the first surface. The second core layer includes a third surface connected to a first grounding layer and a fourth surface corresponding to the third surface. The set of coupled transmission lines includes a plurality of first differential signal lines formed on the second surface with a certain line width and a plurality of second differential signal lines formed on the fourth surface with a line width corresponding to the first differential signal lines. The second surface and the fourth surface are connected to a first dielectric layer making the second surface separated from the fourth surface with an appropriated distance. Moreover, the first differential signal lines and the second differential signal lines are oppositely overlapped with at least a portion of the signal line width.

REFERENCES:
patent: 6645790 (2003-11-01), Moghe et al.

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