Multi-layer staggered power bus layout design

Details Multi-layer staggered power bus layout design Multi-layer staggered power bus layout design

2006-06-27

2006-06-27

Andujar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

C257S691000, C257S700000, C438S128000

Reexamination Certificate

active

07067859

ABSTRACT:
A bus layout design is provided which includes a first electrically conductive layer with a first bus and a second bus and a second electrically conductive layer with a first bus and a second bus. Vias are provided between the first electrically conductive layer and the second electrically conductive layer such that the first bus and the second bus of the first electrically conductive layer are electrically connected.

REFERENCES:
patent: 5311058 (1994-05-01), Smolley
patent: 5723908 (1998-03-01), Fuchida et al.
patent: 5864181 (1999-01-01), Keeth
patent: 6060383 (2000-05-01), Nogami et al.
patent: 6194768 (2001-02-01), Gardner et al.
patent: 6476497 (2002-11-01), Waldron et al.

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