Wave transmission lines and networks – Long line elements and components – Strip type
Reexamination Certificate
2000-01-21
2002-10-15
Bettendorf, Justin P. (Department: 2817)
Wave transmission lines and networks
Long line elements and components
Strip type
C257S728000, C361S795000
Reexamination Certificate
active
06466113
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to communication circuits and components and support structures therefor, and is particularly directed to a new and improved multi-layer printed circuit architecture for high power RF devices that provides low-inductance and low thermal resistance interconnections to a relatively thick, thermal dissipation, ground plane support substrate.
BACKGROUND OF THE INVENTION
Associated with continuing improvements in component micro-miniaturization, integration density and operational frequencies of signal processing and communication circuits, especially those employed in high frequency and high power RF applications, are packaging design and fabrication techniques that will facilitate the practical implementation of an integrated circuit architecture. As diagrammatically illustrated in
FIG. 1
, a typical printed circuit board structure, such as that employed for RF applications, is configured as a multi-layered laminate of dielectric layers (D
1
, D
2
, D
3
) interleaved with patterned conductive layers (L
1
, L
2
, L
3
), which respectively provide RF signaling and shielding, digital and analog control, and DC power functions.
This multi-layer laminate is supported atop a conductive (e.g., copper) ground plane substrate L
4
, that may serve as or be attached to a thermal dissipation medium, serving as a ground plane and mechanically stable support. Integrated circuit components and devices
10
may be surface-mounted to signal traces of the topside patterned conductor layer L
1
formed on the relatively thick dielectric layer D
1
. The multi-layer laminate structure contains a distribution of conductively plated through-holes or vias (one of which is shown at
20
), which provide ‘vertical’ or ‘through-the-stack’ interconnections among the various conductive layers of the laminated structure.
As shown in the interconnect schematic diagram of
FIG. 2
, such plated through-holes typically include the following: 1) through-hole interconnects
21
between the (RF signaling) conductive layer L
1
and the (analog and digital signaling) layer L
3
; 2) through-hole interconnects
22
between (microstrip ground/RF shielding) layer L
2
and the underlying ground plane and thermal dissipation support plate L
4
; and 3) through-hole interconnects
23
among the RF signaling layer L
1
, the microstrip ground layer L
2
and the ground plane and thermal dissipation support plate L
4
.
In order to ensure proper operation of the composite circuit architecture, it is essential to minimize the reactance (parasitic capacitance, and inductance in particular) of interconnects. This mandates the use of shorter sections of conductive material, particularly at higher RF frequencies. Since the effective length of a section of interconnect includes both the vertical plated through-hole dimension and the horizontal dimension of a patterned conductive layer Li to which it is joined, a very efficacious technique to minimize grounding lead inductance is to fabricate such leads as a large number of closely spaced plated ground interconnect vias
22
, that extend between the RF ground/shielding layer L
2
and the bottom ground plate L
4
.
Unfortunately, this gives rise to a significant fabrication issue—ensuring that the plated ground vias
22
between the bottom layer L
4
and RF ground/shield layer L
2
do not extend all the way through the topside dielectric layer D
1
. If they did, the vias
22
would intersect the RF signal trace layer L
1
, and thereby short the RF signaling layer L
1
to ground during a solder reflow step customarily used in the fabrication process. The basic problem is the substantial thickness of the copper substrate L
4
upon which the interleaved dielectric and conductive layer laminate is mounted. In particular, providing the ground interconnects
22
requires the formation of conductive through holes through the stack between the RF shielding layer L
2
and the ground plane layer L
4
.
One way to form the RF shield to ground vias
22
would be to drill holes from the bottom surface of the layer L
4
up into the laminate, so as to intersect the RF shield layer L
2
. However, this approach demands a very exact (and therefore prohibitively expensive) vertical drilling depth through the dielectric—patterned conductor stack. This is especially true, if ground plane layer L
4
has substantial thickness. The hole depths would have to be sufficient to intersect the target RF shield layer L
2
, but not puncture the topside dielectric layer D
1
. It may be noted that the problem cannot be avoided by simply increasing the thickness of the dielectric layer D
1
(in order to increase the tolerance of the drill depth), since the characteristics of the dielectric layers (particularly those of the topside dielectric layer D
1
), including thickness and dielectric properties, must be tailored for proper circuit operation.
SUMMARY OF THE INVENTION
In accordance with the present invention, the above-described problems are effectively obviated by a new and improved multi-layer printed circuit architecture and fabrication process therefor, that facilitates forming a large number of closely spaced plated vias between a robust underlying ground plane support pallet and the RF shielding layer, in a manner that minimizes interconnect inductance, while at the same time preventing unwanted shorting of the RF signal trace layer to ground, during solder reflow for connection to ‘wide lead’ power devices.
By ‘wide lead’ is meant an interconnect medium having a dimension equal to or greater than one-twentieth of a wavelength of propagation within the dielectric material of the RF transmission line. The invention successfully addresses the issue of inductance in the ground return path of the high power device to be mounted in a device well. The sensitivity of the path between the RF shielding layer and the base of the device (which is attached to the underlying ground plane pallet) varies according to the input and output impedances of the device. For large power transistors, these impedances are very low, and the circuit is very sensitive to stray inductance.
As will be described, the multilayer printed circuit structure of the invention includes an interleaved laminate of patterned dielectric layers and patterned conductive layers. The conductive layers are used for RF signaling, RF microstrip shielding/ground, digital and analog control signal leads, and DC power. A vertical interconnect between the RF signaling layer and the control/DC conductive layer is provided by way of a plated bore that intersects material of each of these conductive layers. The RF shielding layer is patterned adjacent to the bore, so as to be laterally offset from bore and thereby prevent conductive material plated in the bore from electrically bridging the RF shielding layer.
A vertical interconnect that joins the RF signaling layer, the RF microstrip shielding layer and the underlying ground plane support pallet is realized by forming a plated bore completely through the laminate structure from the RF signaling layer down through the bottom dielectric layer and into or through the conductive pallet. The support pallet preferably comprises a relatively thick metallic substrate, that is patterned to provide recesses of appropriate depth that conform with each of device capture slots and bores in the laminate structure. Although this bore intersects each of the RF signaling layer and the RF microstrip layer, the DC/control layer is patterned so that the plated bore is laterally offset from it, to prevent the plated bore from contacting the DC/control layer.
In the course of forming a vertical interconnect that electrically joins the RF microstrip shielding layer with the underlying ground plane support pallet, a further bore is drilled completely through the laminate structure from the RF signaling layer down to and at least partially through the ground plane pallet. The further bore intersects each of the RF signaling layer and the microstrip shielding layer; however, the DC
Crescenzi, Jr. E. James
Mohammed Anwar A.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Bettendorf Justin P.
Spectrian Corporation
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