Multi-layer registration control for photolithography processes

Details Multi-layer registration control for photolithography processes Multi-layer registration control for photolithography processes

2000-07-14

2001-04-17

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

C430S030000, C430S005000, C430S022000, C356S401000, C356S399000, C073S105000

Reexamination Certificate

active

06218200

ABSTRACT:

BACKGROUND OF THE INVENTION
1. FIELD OF THE INVENTION
The present invention relates to photolithography processes, and more particularly, to methods and apparatus for multi-layer registration control in a photolithography process.
2. BACKGROUND INFORMATION
In a typical integrated circuit (IC) manufacturing process, a silicon wafer goes through many levels of processing to form the IC. Following a photoprocessing layer, designed circuit patterns are printed on multiple layers of a wafer surface to form the IC. Each layer must be aligned with a prior layer for the IC to operate properly. An overlay controller is generally employed to achieve alignment of two layers within the IC. The accuracy of the overlay controller directly impacts the yield of the IC manufacturing process. As a minimum feature size of the IC shrinks, the tolerance of the overlay controller becomes correspondingly smaller.
Conventional overlay controllers for photolithography processes typically employ a reticle-to-wafer aligner, a stepper, or a scanner. An overlay measurement tool measures overlay errors. Software associated with the overlay controller analyzes the overlay errors that are generated by the overlay measurement tool. The software provides a feedback signal using appropriate correction coefficients to the aligner to correct overlay errors for wafers that are yet to be manufactured. The software generally performs on-line statistical process control (SPC) of overlays on product wafers.
The overlay measurement tool generally uses overlay marks that include overlay portions that are formed on different photolithography processing layers. The overlay marks employed generally have a box-in-box pattern or a frame-in-frame pattern. For example, in the box-in-box pattern, an outer box is printed on one layer and an inner box is printed on another layer. When the IC includes three or more layers that require overlay error measurement, two or more pairs of overlay marks are typically required. The overlay marks are placed in a scribe grid area of the wafer that reduces the available area for integrated circuits. As the scribe grid increases, the cost of each IC increases. Clearly a need exists for improved registration control for photolithography processes.


REFERENCES:
patent: 5498500 (1996-03-01), Bae
patent: 5756238 (1998-05-01), Barr et al.
patent: 5952132 (1999-09-01), King et al.
patent: 6023338 (2000-02-01), Bareket
patent: 6079256 (2000-06-01), Bareket
patent: 6127075 (2000-10-01), Hsu
patent: 6128089 (2000-10-01), Ausschnitt
patent: 6137578 (2000-10-01), Ausschnitt

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