Multi-layer registration and dimensional test mark for...

Details Multi-layer registration and dimensional test mark for... Multi-layer registration and dimensional test mark for...

2007-06-26

2009-02-17

Nguyen, Sang (Department: 2886)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257SE23007

Reexamination Certificate

active

07492049

ABSTRACT:
A layered test pattern for measuring registration and critical dimension (CD) for multi-layer semiconductor integrated circuits is disclosed. A first layer includes a first pattern having vertical and horizontal portions. A second layer is formed over the first layer and includes a second pattern having vertical and horizontal portions having nominal vertical and horizontal phase shifts with respect to the vertical and horizontal portions, respectively, of the first pattern. The vertical and horizontal portions include periodically repeating vertical lines and horizontal lines, respectively. The nominal phase shifts may be half of the period of the vertical and horizontal lines. A scatterometry tool measures the width of the lines and the phase shift of the first pattern relative to the second pattern. The width of the lines corresponds to CD, whereas the difference between the measured phase shift and the nominal phase shift indicates variation in registration.

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