Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1998-10-05
2001-01-16
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000, C361S780000, C361S794000
Reexamination Certificate
active
06175088
ABSTRACT:
TECHNICAL FIELD
This invention relates to the configuration of multi-layer printed-wiring boards (PWBs), also known as printed-circuit (PC) boards.
BACKGROUND OF THE INVENTION
The problem of routing conductive traces in densely-packed PWBs has been at the forefront of electronics circuit design and manufacture for decades. On multi-layer PWBs, most of the traces lie on between the internal conductive layers of the PWB. In order to effect connections between the conductive layers, conductive vias are required. Vias have traditionally been formed as through-hole vias: by drilling holes through the entire PWB after the multiple layers have been assembled and then plating the holes with a conductive material, such as copper, so as to connect traces or solder pads on one layer to those on another one or more layers. During the PWB design process, as more and more vias are placed on the PWB, the task of routing the traces on the various conductive layers becomes more and more difficult, because the vias represent blockages for traces that do not connect to them. The recent introduction of ball-grid array (BGA) devices, whose “pins” (solder balls) are arranged in a tightly-packed two-dimensional array, exacerbate this routing problem, because the density of the “pin” array creates a virtual “bed-of-nails” via structure within the PWB. Such a large number of obstructions can make the routing problem virtually impossible to solve.
Recently, a significant improvement in via technology has been introduced, called micro-via. Micro-vias are very small blind vias. A blind via is one that extends from a surface of the completed PWB to one of the interior conductive layers of the PWB. The holes for micro-vias are typically laser-drilled for precision and for lower cost. Such micro-vias do not create blockages on PWB layers to/through which they do not extend. Nevertheless, they create as much of an obstruction in the layers through which they do extend as the through-hole vias.
Blind vias can be created by controlling drill depth or by drilling a laminated sub-component of a multi-layer PWB prior to final lamination. The latter adds cost to the assembly process and does not afford the opportunity to connect buried vias to blind vias. The former technique has been viable with mechanical drills, but only for relatively large-dimensioned PWB designs, due to loose mechanical tolerances.
Vias, whether through-hole or blind, generally attach to a layer at a pad, as do the contacts (“pins”) of components at the outer surface layers of the PWB. However, if the contact of a component is attached to the same pad as a via, there is the danger—which increases with the diameter of the via—that the via will wick the solder away from the contact and thereby cause an unreliable connection. For this reason, separate pads have generally been used on the outer surface layers of the PWB for attaching vias and for attaching component contacts. But, like the vias, the additional pads create routing blockages on the surface layers of the PWB and they limit the number of connections that can be made to, and hence the number of components that can be mounted on, the PWB. It is therefore desirable to put vias in the component pads, if the solder-wicking problem can be overcome, so as to allow additional trace routing on the outer surface layers.
SUMMARY OF THE INVENTION
This invention is directed to solving these and other problems and disadvantages of the prior art. Generally according to the invention, the inventor has combined the use of micro-vias with carefully-selected placement of power and ground layers within the PWB to minimize the trace-routing blockages caused by vias.
According to one aspect of the invention, in a multi-layer printed-wiring board, the ground layer and the power layer are placed directly adjacent to each other and to the outer surface layer, i.e., without intermediacy of any other conductive layer, and the outer surface layer is conductively connected to the power and ground layers by vias that do not extend to any other conductive layers, e.g., signal-routing inner layers that are placed below the power and ground layers. Thus, the connections between the outer surface layer and the power and ground layers avoid causing trace-routing blockages on the other layers. The printed-wiring board may have components mounted on both outer surfaces (top and bottom), in which case it also has a second ground layer and a second power layer placed directly adjacent to each other and to the second outer surface layer, i.e., without intermediacy of any other conductive layer, and the second outer surface layer is conductively connected to the second power and ground layers by second vias that do not extend to any other conductive layers.
According to another aspect of the invention, in a multi-layer printed-wiring board, a first one (e.g., a power layer and/or a ground layer) of a plurality of inner conductive layers is positioned adjacent to an outer surface layer and defines a plurality of elongated pads that have a first region and a second region separated from the first region. Illustratively, each elongated pad is a double pad that comprises a pair of adjacent and conductively interconnected single pads, with different pads of the pair forming the first and the second regions. The elongated pads correspond to different pads on the outer surface layer, which are for having connections made thereto, e.g., leads of electrical components soldered thereto or test probes contacted therewith. The outer surface layer further defines a plurality of conductive micro-vias, each extending between and connecting a different one of the surface pads to the first region of the corresponding elongated pad. The micro-vias do not extend to inner conductive layers beyond the first inner layer. The inner layers define a plurality of conductive buried vias that extend between and connect the second regions of the elongated pads to signal routing traces on the inner conductive layers. By definition, the buried vias do not extend to the outer surface layer. The use of the micro-vias to connect to the surface pads solves the problem of vias wicking solder away from component leads. The use of the elongated pads solves the problem of connecting micro-vias to through-hole vias (called “the stacked via problem”). And the placement of the elongated pads on one of the first inner conductive layers solves both the problem of the micro-vias having shallow penetration into a board and the trace-routing blockages that would be caused by placement of the elongated pads on the outer surface layer.
These and other features and advantages of the present invention will become more apparent from the following description of an illustrative embodiment of the invention taken together with the drawing.
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Avaya Technology Corp.
Cuneo Kamand
Gaffin Jeffrey
Volejnicek David
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