Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2001-04-11
2003-06-17
Talbott, David L. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000
Reexamination Certificate
active
06580036
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-layer printed circuit board, and more particularly, to a multi-layer printed circuit board having a plurality of bump connection pads for mounting a Ball Grid Array Packaging type semiconductor component, and its fabrication method. The present invention also relates to a printed circuit board having a thin printed circuit board compared to that of conventional art and which is capable of solving a problem of defective attachment of a bump due to a void in a blind via hole (referred to as ‘BVH’, hereinafter).
2. Description of the Background Art
FIG. 1
is a sectional view of a multi-layer printed circuit board in accordance with the conventional art.
As shown in the drawing, a plurality of resin layers
3
a
and
3
b
are stacked by a built-up method, and circuit patterns
5
a
,
5
b
and
5
c
made of metal thin layer are formed on each resin layer
3
a
and
3
b.
A blind via hole
7
b
is formed penetrating the resin layer to connect the upper circuit pattern
5
c
and the lower circuit pattern
5
a
. The blind via hole
7
b
is formed having a reversed conical shape wherein the diameter of the entrance is greater than that of the bottom. The entrance of the upper via hole
7
b
and the lower via hole
7
a
is positioned in the same direction (the upward direction in FIG.
1
).
Plated layers
9
a
and
9
b
are formed at the inner side of the blind via holes
7
a
and
7
b
, respectively. The plated layer
9
a
,
9
b
are also extendedly formed on the upper surface of the upper circuit pattern
5
c
and the lower circuit pattern
5
a
. Thus, the upper circuit pattern
5
c
and the lower circuit pattern
5
a
are electrically connected by the plated layers
9
a
,
9
b.
An inner lead bump
11
for electrical connection with a semiconductor chip component (now shown) is attached at the upper portion of the plated layer
9
b
on the upper surface of the blind via hole
7
b.
A solder resist layer
12
covers the upper surface of the plated layer
9
b
and the resin layer
3
b
except for the portions where the inner lead bump
11
is attached. That is, in the conventional multi-layer printed circuit board of
FIG. 1
, the inner lead bump
11
is attached in the blind via hole.
A method for fabricating the above described printed circuit board will now be explained.
First, a cooper clad laminate (CCL) is prepared wherein an upper metal thin plate
4
a
and a lower metal thin plate
4
b
are coated on both surfaces of the lower resin layer
3
a.
The upper metal thin plate
4
a
and the lower resin layer
3
a
are etched to form a lower blind via hole
7
a
. The lower plated layer
9
a
is formed at the side wall face and the bottom surface of the lower blind via hole
7
a
to electrically connect the upper and the lower metal thin plates
4
a
,
4
b.
Thereafter, the upper metal thin plate
4
a
and the lower plated layer
9
a
are patterned to form the lower circuit pattern
5
a.
Next, the resin layer
3
b
and a metal film
4
c
are formed at the upper surface of the lower plated layer
9
a
and the lower resin layer
3
a.
And then, the metal film
4
c
and the upper resin layer
3
b
are partially etched to form the upper blind via hole
7
b
. At this time, the upper surface of the lower circuit pattern
5
a
is exposed through the upper blind via hole
7
b.
And, the upper plated layer
9
b
is formed at the upper surface of the metal film
4
c
, at the inner wall face of the upper blind via hole
7
b
and at the upper surface of the lower plated layer
9
a
exposed at the bottom of the upper blind via hole
7
b.
Then, the upper plated layer
9
b
and the metal film
4
c
are patterned. The patterned metal film
4
c
becomes the upper circuit pattern
5
c
. The upper circuit pattern
5
c
and the lower plated layer
9
a
are electrically connected by the upper plated layer
9
b.
Next, the solder resist layer
12
is formed at the upper surface of the upper plated layer
9
b
and at the exposed upper resin layer
3
b
except for the inside of the upper blind via hole
7
b
. The upper surface of the upper plated layer
9
b
, which is exposed by not being covered with the solder resist layer
11
, is a pad for attaching a bump for mounting a chip component.
And then, the solder bump
13
is attached at the upper surface of the upper plated layer
9
b
within the upper blind via hole
7
a
, that is, at the pad.
However, the printed circuit board fabricated according to the conventional method has the following problems.
For example, first, since the bump
13
is formed at the upper portion of the upper blind via hole
7
b
, the air in the upper blind via hole
7
b
is not discharged externally, forming an air void
14
, or the air flows into the bump
13
and remains there. Then, due to the heat generated in mounting a chip component on the printed circuit board or from the intense heat generated from use of its product, the blind via hole or the air void of the bump swells to generate a crack to the printed circuit board around the bump or to deteriorate the attachment state of the chip components, resulting in damage to the packaging state of the chip components of the printed circuit board.
Secondly, in an effort to solve the problem, a Japanese Patent Laid Open No. 10-284846 discloses a method in which, for mounting the bump, the pad is extendedly designed in the vicinity of the blind via hole, avoiding the blind via hole. In this case, however, a problem arise in that the printed circuit board increases in size.
Thirdly, in a flip chip fabricating process, when an under filler is filled between the chip and the printed circuit board to correct a difference in the heat expansion between the chip mounted on the printed circuit board and the printed circuit board, the under filler is not completely filled in the blind via hole
7
, causing a problem in that the printed circuit board is deformed due to thermal impact.
Lastly, in the case of forming a flexible printed circuit board, if the resin layer is too thin, it is inconvenient to handle it during the fabricating process, degrading yield rate. A solution to this problem is to forming the resin thick, but it is difficult to decrease the thickness of the printed circuit board.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide an ultra-thin flexible printed circuit board.
Another object of the present invention is to provide a printed circuit board having a relatively fine circuit pattern which is formed at an outer layer thereof.
Still another object of the present invention is to provide a printed circuit board in which a solder bump and an inner lead, is formed at the opposite side of an opening of a blind via hole.
Yet another object of the present invention is to provide a printed circuit in which an opening of a blind via hole is directed to the center rather than to the outer surface thereof.
Still yet another object of the present invention is to provide a printed circuit board in which a circuit pattern to be formed at the upper surface thereof is thinner than a circuit pattern to be formed at the lower surface connected to a pain printed circuit board.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a multi-layer printed circuit board on which insulation resin layers and circuit pattern layers are alternatively stacked to form multiple layers, including: an insulation resin layer; a circuit pattern formed at the upper surface of the insulation resin layer; a blind via hole formed by penetrating the insulation resin layer and the circuit pattern; a plated layer formed at the upper surface of the circuit pattern, at the inner wall face and the bottom of the via hole; an inner lead bump pad formed at the surface of the plated layer which is exposed to the lower surface of the insulation resin layer; and an outer lead bump pad formed on the circuit pattern which is formed at th
Kim Dock-Heung
Kim Yong-Il
Birch & Stewart Kolasch & Birch, LLP
LG Electronics Inc.
Norris Jeremy
Talbott David L.
LandOfFree
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