Multi-layer metallization capacitive structure for reduction...

Details Multi-layer metallization capacitive structure for reduction... Multi-layer metallization capacitive structure for reduction...

1998-04-06

2001-03-20

Kincaid, Kristine (Department: 2831)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C361S301400, C361S301200, C361S311000

Reexamination Certificate

active

06205013

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87102003, filed Feb. 13, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to noise reduction means in integrated circuits, and more particularly, to a multi-layer metallization capacitive structure which can help reduce the simultaneous switching noise (SSN) due to rapid switching of pulses in a digital signal.
2. Description of Related Art
The SSN effect is caused by the rapid switching of the pulses in a digital signal due to the inductance of the conductive line or the ground line.
FIG. 1
shows a CMOS inverter in which the SSN effect is a problem. As shown, the CMOS inverter includes a PMOS transistor (P-type metal-oxide semiconductor transistor)
10
and an NMOS transistor (N-type metal-oxide semiconductor transistor)
12
. The gate of the PMOS transistor
10
and the gate of the NMOS transistor
12
are tied together and connected to the input port for receiving a stream of pulses representative of digital data or signals. The source of the PMOS transistor
10
is connected via a power line
18
and a first inductor
14
to a system voltage V
d
, where, for example, V
d
=5 V (volt). The source of the NMOS transistor
12
is connected via a ground line and a second inductor
16
to the ground. Further, the drain of the PMOS transistor
10
and the drain of the NMOS transistor
12
are tied together and connected to the output port of the inverter.
One drawback to the foregoing circuit, however, is that when the pulses in the input signal are switched from one state to the other, an instantaneous current will be induced to flow either through the first inductor
14
to the system voltage line or through the second inductor
16
to the ground. A high voltage is thus induced across the power line
18
due to the instantaneous change in the current. This can be represented by the following relationship:
&Dgr;
V=L·dI/dt.
where
&Dgr;V is the induced voltage;
L is the inductance of the power line; and
dI/dt is the rate of change of the instantaneous current.
The induced high voltage from the power line would then influence the neighboring circuits that are connected to the inverter. The influence from such a high voltage is particularly adverse in integrated circuits of high packing densities and small sizes; high voltage can corrupt the digital data that are processed by the integrated circuits.
One solution to the foregoing problem, as shown in
FIG. 1
, is to provide a so-called on-chip capacitor
15
across the source and drain of the NMOS transistor
12
to offset the inductance of the conductive line connected to the ground. This provision can suppress the instantaneous current to a lesser degree. A conventional structure for forming the on-chip capacitor
15
in an integrated circuit is depicted in the following with reference to FIG.
2
.
In
FIG. 2
, the reference numeral
20
designates a power line or a ground line where the problem of the SSN effect is serious. As shown, the on-chip capacitor
15
includes a first metallization layer
22
connected to the power line or the ground line
20
, a second metallization layer
24
formed beneath the first metallization layer
22
, and a dielectric layer
26
sandwiched between the first and second metallization layers
22
,
24
.
The foregoing on-chip capacitor structure has two major drawbacks. First, it takes quite a large layout space in the integrated circuit, which is cost-ineffective for the manufacture of integrated circuits. Second, since the level of SSN is difficult to precisely predict in advance, if the on-chip capacitor fails to suppress the SSN effect, the whole layout should be redesigned. This makes the manufacture of the integrated circuits even more cost-ineffective.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a multi-layer metallization capacitive structure, which can help reduce the simultaneous switching noise in an integrated circuit.
It is another objective of the present invention to provide a multi-layer metallization capacitive structure, which will take up a lesser layout space in the integrated circuit as compared to the prior art.
In accordance with the foregoing and other objectives of the present invention, an improved multi-layer metallization capacitive structure is provided. The multi-layer metallization capacitive structure of the invention includes a power line, at least one metallization layer which extends substantially beneath the power line and at least one dielectric layer sandwiched between the power line and the metallization layer. The multi-layer metallization capacitive structure can provide the optimal effect if the metallization layer is designed to be precisely equal in width to the power line.


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