Multi-layer metal wiring of semiconductor device preventing...

Details Multi-layer metal wiring of semiconductor device preventing... Multi-layer metal wiring of semiconductor device preventing...

2011-08-30

2011-08-30

Nguyen, Dao H (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

Reexamination Certificate

active

08008774

ABSTRACT:
A multi-layer metal wiring of a semiconductor device and a method for forming the same are disclosed. The multi-layer metal wiring of the semiconductor device includes a lower Cu wiring, and an upper Al wiring formed to be contacted with the lower Cu wiring, and a diffusion barrier layer interposed between the lower Cu wiring and the upper Al wiring. The diffusion barrier layer is formed of a W-based layer.

REFERENCES:
patent: 5572072 (1996-11-01), Lee
patent: 6797642 (2004-09-01), Chu et al.
patent: 2004/0203223 (2004-10-01), Guo et al.

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