Multi-layer metal capacitor

Details Multi-layer metal capacitor Multi-layer metal capacitor

1999-01-12

2001-03-06

Dinkins, Anthony (Department: 2836)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C361S303000, C361S306300, C361S312000, C361S313000, C257S303000, C257S306000

Reexamination Certificate

active

06198617

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a structure of manufacturing a capacitor. More particularly, the present invention relates to a structure for forming a stack of multi-layer metal capacitors.
2. Description of Related Art
Most analog or mixed mode circuits in a semiconductor chip contain capacitors. At present, most capacitors are of the double-polysilicon capacitor (DPC) type as shown in FIG.
1
. As shown in
FIG. 1
, a double-polysilicon capacitor
100
is a capacitor having an upper electrode
104
and a lower electrode
102
, both fabricated from polysilicon material. There is a dielectric layer
106
between the upper electrode
104
and the lower electrode
102
. N-type impurities, for example, can be doped into the polysilicon layer to increase its electrical conductivity. In general, the lower electrode
102
of the double-polysilicon capacitor
100
is connected to a ground terminal while the upper electrode
104
is connected to a negative bias voltage V
bias
. Hence, when the capacitor
100
is being charged, holes within the polysilicon lower electrode
102
migrate to a region on the upper surface of the lower electrode due to the negative bias voltage V
bias
. These holes compensate for the N-type impurities originally doped inside the polysilicon electrode
102
. Consequently, a depletion region
108
is formed on the upper surface of the electrode
102
, thus forming an additional dielectric layer. In other words, an additional dielectric layer is formed over the original dielectric layer
106
, thereby thickening the overall dielectric layer and reducing the charge storage capacity of the capacitor. Furthermore, capacitance of the capacitor is unstable due to some minor fluctuation of the negative bias voltage V
bias
too.
In addition, the double-polysilicon capacitor is formed by providing a first polysilicon layer, and then depositing a dielectric layer over the first polysilicon layer. Finally, one more polysilicon deposition process has to be carried out. The entire fabrication process is long and involves many steps. Moreover, conventional capacitor structure tends to occupy a larger chip area, thereby compromising the effort to increase the level of integration through a reduction in device dimensions.
In light of the foregoing, there is a need to provide an improved capacitor structure.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a structure of a capacitor capable of preventing a reduction in storage capacity due to a thickening of the dielectric layer when bias voltage is applied to the capacitor during operation.
In another aspect, the purpose of the invention is to provide a simpler method of forming the capacitor, which method is capable of shortening processing time and reducing production cost. Furthermore, the capacitor formed by this method has a structure that occupies less space, and thereby is capable of increasing the level of device integration.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a structure of a capacitor includes an electromigration layer, which is located on a dielectric layer and serves as a lower electrode of the capacitor. A patterned capacitor dielectric layer is located on the electromigration layer, and a patterned metallic layer is located on the capacitor dielectric layer and serves as an upper electrode of the capacitor.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4638400 (1987-01-01), Brown et al.
patent: 4742018 (1988-05-01), Kimura et al.
patent: 5479316 (1995-12-01), Smrtic et al.
patent: 5563762 (1996-10-01), Leung et al.
patent: 5621606 (1997-04-01), Hwang
patent: 5801399 (1998-09-01), Hattori et al.
patent: 5838032 (1998-11-01), Ting
patent: 6040616 (2000-03-01), Dennis et al.

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