Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2002-11-27
2004-03-16
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S666000, C257S667000, C257S668000, C257S675000, C257S676000, C257S692000, C257S723000
Reexamination Certificate
active
06707136
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to a semiconductor lead package system and, more particularly, to a multilayer lead frame for decoupling the power supply to an integrated circuit chip.
2. State of the Art
A semiconductor integrated circuit (IC) packaged device (part) generally includes an IC chip (die) being connected to inner leads of a lead frame by wire bonds. The chip, wire bonds, and inner leads are completely encapsulated for protection with a substance, such as plastic. Outer leads communicate with the inner leads of the lead frame, but the outer leads typically remain exposed for mounting of the packaged device to external circuitry, such as a printed circuit board.
In a conventional IC packaged device, a semiconductor die is placed on and bonded to a center die paddle of a lead frame for support. Inner lead fingers of the lead frame are disposed proximate to the paddle but do not contact or communicate with the paddle. Rather, wire bonds communicate between contact pads (terminals) on the die and the inner lead fingers of the lead frame by spanning the gap between the die and the fingers. The wire bonds allow for the transmission of the electrical signals between the die and the lead frame.
The recent production of three (3) volt IC chips has created the need for better power supply stability when testing and using the parts. Small spikes, glitches, bounces, noise, or the like (collectively “distortions”) on the power supply are more likely to cause failure in these 3-volt parts than in five (5) volt parts which have a better margin of error for power supply distortions. Namely, a given distortion at 3 volts is a higher percentage of the overall voltage than that at 5 volts.
In an effort to resolve potential failure from voltage distortions, decoupling capacitors have been mounted externally to the part on a board, or mounted on a handler during testing, in order to ensure a cleaner voltage supply to the part. However, for best decoupling, a capacitor must be mounted as close to the part as possible. But in an effort to mount a capacitor close to a part, other drawbacks usually arise. For example, a capacitor can be embodied on a die, but this takes up valuable and limited die space. Also, when testing a part in a handler, it is difficult to mount a capacitor close enough to the part to provide a reasonable amount of decoupling.
Thus, in an attempt to provide power supply decoupling, and also to improve heat dissipation and electrical performance, it has been known to use a multilayer lead frame wherein one of power supply and ground connections is supplied through a first layer, and the other of power supply and ground connections is supplied through a second layer. For example, U.S. Pat. No. 4,891,687 issued to Mallik et al. on Jan. 2, 1990, discloses a multilayer IC package. However, this disclosure requires the use of two conductive plates overlaying each other for power and ground, respectively, and a separate lead frame overlaying the plates for wire bonding. As such, the solution is undesirably complex. Namely, two separate layers of adhesive must bond the two plates and lead frame, one plate must have a center portion punched out for placement of the die and for wire bonding the die with the plates, and special tabs must be placed in precise locations on the plates for electrically connecting the plates with lead fingers of the lead frame.
Similarly, U.S. Pat. No. 4,965,654, issued to Karner et al. on Oct. 23, 1990, discloses a semiconductor package with a ground plane. However, in this case, the adaptation is only for a Lead Over Chip (LOC) implementation, and there are not two separate plates for power supply and ground connections, but rather only a ground plane and a lead frame overlaying the ground plane. Consequently, the decoupling capacitive effect is not as complete. Furthermore, the ground plane is actually two separate plates overlaying the die and proximate the bonding pads. This is necessary in order to allow for wire bonding of the lead fingers with the centrally located pads on the die. Moreover, the ground plane has special, small, cut-away portions on a surface for wire bonding with the die.
Given the foregoing problems associated with existing art and techniques, objects of the present invention are to provide a semiconductor lead package system that provides good decoupling of a power supply to a semiconductor die with a simplified multilayer lead frame.
BRIEF SUMMARY OF THE INVENTION
According to principles of the present invention in its preferred embodiment, a multilayer lead frame for decoupling a power supply to a semiconductor die includes overlaying first and second lead frame bodies having an insulator disposed therebetween and at least one main lead finger extending from each body. The bodies act as a capacitor to decouple the power supply to the die. One of the bodies and a respective finger provides one of power supply and ground connections for wire bonding with the die, and the other of the bodies provides the other of power supply and ground connections for wire bonding with the die.
According to further principles of the present invention, the first body includes a die paddle for supporting the die, and the second body includes a plate. The paddle overlays the plate with the insulator disposed in between the paddle and plate, thereby providing an electrical decoupling effect therebetween upon supplying power and ground connections respectively.
According to further principles of the present invention, a method of decoupling a power supply is disclosed for a semiconductor die using a multilayer lead frame as disclosed herein. The method comprises the steps of (1) supplying one of a power signal and a ground connection to the die through the first main lead finger extending from one of the paddle and plate, and wherein a wire bond communicates between the first main lead finger and one of a power and ground terminals of the die, and (2) supplying the other of the power signal and ground connection to the die through the second main lead finger extending from the other of the paddle and plate, and wherein a wire bond communicates between the second main lead finger and the other of the power and ground terminals of the die.
The aforementioned principles of the present invention provide an improved multilayer lead frame for decoupling a power supply to a semiconductor die. Other objects, advantages, and capabilities of the present invention will become more apparent as the description proceeds.
REFERENCES:
patent: 4410905 (1983-10-01), Grabbe
patent: 4680613 (1987-07-01), Daniels et al.
patent: 4891687 (1990-01-01), Mallik et al.
patent: 4965654 (1990-10-01), Karner et al.
patent: 4984059 (1991-01-01), Kubota et al.
patent: 4994936 (1991-02-01), Hernandez
patent: 5032895 (1991-07-01), Horiuchi et al.
patent: 5095402 (1992-03-01), Hernandez et al.
patent: 5103283 (1992-04-01), Hite
patent: 5105257 (1992-04-01), Michii
patent: 5140496 (1992-08-01), Heinks et al.
patent: 5200364 (1993-04-01), Loh
patent: 5212402 (1993-05-01), Higgins, III
patent: 5235209 (1993-08-01), Shimizu et al.
patent: 5237202 (1993-08-01), Shimizu et al.
patent: 5281556 (1994-01-01), Shimizu et al.
patent: 5291060 (1994-03-01), Shimizu et al.
patent: 5311056 (1994-05-01), Wakabayashi et al.
patent: 5365106 (1994-11-01), Watanabe
patent: 5734198 (1998-03-01), Stave
patent: 6124630 (2000-09-01), Stave
patent: 6150715 (2000-11-01), Ichikawa et al.
patent: 6153924 (2000-11-01), Kinsman
patent: 6307255 (2001-10-01), Stave
patent: 3626151 (1988-02-01), None
patent: 6393139 (1988-04-01), None
patent: 3165549 (1991-07-01), None
patent: 3276747 (1991-12-01), None
patent: 4162657 (1992-06-01), None
patent: 4188759 (1992-07-01), None
patent: 6045504 (1994-02-01), None
Hyperquad Series Type 5, Three Metal Layer QFP (TM QFP), 2 pages.
Micro)n Technology, Inc.
Tran Mai-Huong
TraskBritt
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