Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-10-05
2003-10-28
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S758000
Reexamination Certificate
active
06639298
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to inductors formed on an integrated circuit substrate, and more specifically to inductors having a core spanning at least three metal layers of the integrated circuit.
BACKGROUND OF THE INVENTION
The current revolution in wireless communications and the need for smaller wireless communications devices has spawned significant efforts directed to the optimization and miniaturization of radio communications electronics devices. Passive components of these devices (such as inductors, capacitors and transformers), play a necessary role in the devices' operation and thus efforts are directed toward reducing the size and improving the fabrication efficiency of such components.
Inductors, which play an integral role in the performance of electronic communications devices, are electromagnetic components comprising a plurality of windings typically enclosing a core constructed of either magnetic material or an insulator. Use of a magnetic core yields higher inductance values. The inductance is also substantially affected by the number of coil turns; specifically, the inductance is proportional to the square of the number of turns. The inductance value is also affected by the radius of the core and other physical factors. Conventional inductors are formed as a helix (also referred to as a solenoidal shape) or a torroid.
With the continual allocation of operational communications frequencies into higher frequency bands, inductor losses increase due to increased eddy current and skin effect losses. For use in devices operating at relatively low frequency, inductors can be simulated by employing certain active devices. But simulated inductors are more difficult to realize at higher frequencies, have a finite dynamic range and inject additional and unwanted noise into the operating circuits.
The Q (or quality factor) is an important inductor figure of merit. The Q measures the ratio of inductive reactance to inductive resistance. High Q inductors present a narrow peak when the inductor current is graphed as a function of the input signal frequency, with the peak representing the frequency at which the inductor resonates. High Q inductors are especially important for use in frequency-dependent circuits operating with narrow bandwidths. Because the Q value is an inverse function of inductor resistance, it is especially important to minimize the resistance to increase the Q.
Most personal communications devices incorporate integrated circuit active components fabricated using semiconductor technologies, such as silicon or gallium-arsenide. The prior art teaches certain integrated planar inductors (including torroidal or spiral shapes) developed to achieve compatibility with the silicon-based integrated circuit fabrication processes. However, such planar inductors tend to suffer from high losses and low Q factors at the operative frequencies of interest. These losses and low Q factors are generally attributable to dielectric losses caused by parasitic capacitances and resistive losses due to the use of thin and relatively high resistivity conductors. Another disadvantage of conventional planar inductors is due to the magnetic field lines perpendicular to the semiconductor substrate surface. These closed-loop magnetic field lines enter the material above, beside and below the inductor. Penetration of the dielectric materials increase the inductive losses and lowers the inductor's Q factor. Also, unless the inductor is located at a significant distance from the underlying active circuit elements formed in the silicon, the inductor magnetic fields induce currents in and therefore disrupt operation of the underlying active components.
With integrated circuit active devices growing smaller and operating at higher speeds, the interconnect system should not add processing delays to the device signals. Use of conventional aluminum interconnect metallization restricts circuit operational speed as the longer interconnects and smaller interconnect cross-sections increase the interconnect resistance. Also, the relatively small contact resistance between the aluminum and silicon surfaces creates a significant total resistance as the number of circuit components grows. It is also difficult to deposit aluminum with a high aspect ratio in vias and plugs, where the aspect ratio is defined as the ratio of plug thickness to diameter.
Given theses disadvantages, copper is becoming the interconnect of choice because it is a better conductor than aluminum (with a resistance of 1.7 micro-ohm cm compared to 3.1 micro-ohm cm for aluminum), is less susceptible to electromigration, can be deposited at lower temperatures (thereby avoiding deleterious effects on the device dopant profiles) and is suitable for use as a plug material in a high aspect ration plug. Copper interconnects can be formed by chemical vapor deposition, sputtering, electroplating and electrolytic plating.
The damascene process is one technique for forming active device copper interconnects. A trench is formed in a surface dielectric layer and the copper material is then deposited therein. Usually the trench is overfilled, requiring a chemical and mechanical polishing step to re-planarize the surface. This process offers superior dimensional control because it eliminates the dimensional variations introduced in a typical pattern and etch interconnect process. The dual damascene process extends the damascene process, simultaneously forming both the underlying vias and the interconnecting trenches from copper. First the plug via and then the metal trench is formed. A subsequent metal deposition step fills both the via and the trench, forming a complete metal layer. A chemical and mechanical polishing step planarizes the top surface or the substrate.
U.S. Pat. No. 6,008,102 describes one process for forming a three-dimensional or helical inductor using copper layers formed by conventional and multiple patterning, etching and deposition steps. The multiple interconnecting vias are formed and filled with metal in separate steps from the formation and filling of the trenches.
BRIEF SUMMARY OF THE INVENTION
To provide further advances in the fabrication of inductors in conjunction with active devices on a semiconductor substrate, an architecture and processes is provided for forming such an inductor within the conventional metal layers of an integrated circuit, wherein the inductor core area is larger than prior art inductors, resulting in a higher inductance value and a higher Q figure of merit. Also, an inductor formed according to the teachings of the present inventions has a desirable low-resistance (and thus high Q) in a relatively compact area of the integrated circuit. One technique for forming such an inductor is a dual damascene process.
According to one embodiment of the invention, a plurality of parallel lower conductive strips are formed overlying the semiconductor substrate, in which active components were previously formed. First and second vertical conductive via openings are formed over first and second opposing edges of each lower conductive strip and conductive material is deposited within the via openings to form first and second conductive vias. Two additional via openings are formed in vertical alignment with the first and the second conductive vias and filled with metal to form third and fourth conductive vias. A plurality of upper conductive strips are then formed, wherein the plane of an upper conductive strip intersects the plane of a lower conductive strip such that a first edge of one upper conductive strip overlies the first edge of a lower conductive strip, and the two edges are interconnected by the first and the third conductive vias. A second edge of the upper conductive strip overlies the second edge of the next parallel lower conductive strip, and these edges are electrically connected by the second and the fourth conductive vias. Thus the inductor comprises a helix of individual windings.
According to another embodiment of the invention, a plurality of parall
Chaudhry Samir
Griglione Michelle D.
Laradji Mohamed
Layman Paul Arthur
Thomson J. Ross
Agere Systems Inc.
Beusse Brownlee Bowdoin & Wolter P.A.
DeAngelis Jr. John L.
Wilson Allan R.
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