Multi-layer fin wiring interposer fabrication process

Details Multi-layer fin wiring interposer fabrication process Multi-layer fin wiring interposer fabrication process

2007-08-07

2010-11-16

Sandvik, Benjamin P (Department: 2826)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

C257S758000, C257SE21507

Reexamination Certificate

active

07833835

ABSTRACT:
An interposer having multi-layer fine wiring structure which comprises an insulating layer made of photosensitive polyimide which is photosensitive organic material and a wiring layer portion made of metal, such as copper, silver, gold, aluminum, palladium, indium, titanium, tantalum, and niobium, functions as wiring in an integrated circuit chip, wherein junctions between the integrated circuit chip and the interposer are formed by micron to submicron size fine connection metal pads or bumps which are formed on both the integrated circuit chip and the interposer.

REFERENCES:
patent: 3822467 (1974-07-01), Symersky et al.
patent: 5321210 (1994-06-01), Kimbara et al.
patent: 6246102 (2001-06-01), Sauerbrey et al.
patent: 6462427 (2002-10-01), Sakiyama et al.
patent: 6591491 (2003-07-01), Fujii et al.
patent: 6627377 (2003-09-01), Itatani et al.
patent: 7057279 (2006-06-01), Ogawa
patent: 2001/0012596 (2001-08-01), Kunimoto et al.
patent: 2002/0071256 (2002-06-01), Figueroa et al.
patent: 2002/0109232 (2002-08-01), Lin et al.
patent: 2002/0160600 (2002-10-01), Eckert et al.
patent: 08-279672 (1996-10-01), None
patent: 2000-299505 (2000-10-01), None
patent: 2001-102479 (2001-04-01), None
patent: 3213722 (2001-07-01), None
patent: 2003-309121 (2003-10-01), None
patent: 2004-047744 (2004-02-01), None
Office Action mailed on Oct. 23, 2007 (Japan).
Takahashi et al., “Current Status of Research and Development for Three-Dimensional Chip Stack Technology,” Japan Journal of Applied Physics, vol. 40, Pt. 1, No. 4B, pp. 3032-3037, The Japan Society of Applied Physics (Apr. 2001).

Affiliated with

Also associated with

Rating

Multi-layer fin wiring interposer fabrication process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-layer fin wiring interposer fabrication process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-layer fin wiring interposer fabrication process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4214509