Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-12-20
2002-03-26
Sircus, Brian (Department: 2839)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C361S767000
Reexamination Certificate
active
06362435
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a conductor pad of which reduces the occurrence of gas voids in solder.
BACKGROUND OF THE INVENTION
Microelectronic devices are being increasingly incorporated into electronic systems designed to handle power control and switching operations. Such microelectronic power devices include bipolar transistors and related devices, insulated-gate bipolar transistors, Darlington transistors, SCRs, gate turn-off thyristors, TRIACs, various types of FETs, power MOSFETs, insulated gate field-effect transistors, and hybrids or other devices related to the same.
Such microelectronic power devices are commonly mass-produced as integrated circuits (ICs) fabricated on silicon wafers. An exemplary silicon wafer may be from 4 to 12 inches in diameter and have an array of as many as several hundred separate device locations on the wafer wherein each location contains an individual microelectronic power device. Typically, the wafer will have one or more layers of standard metallization on its underside. Once the individual microelectronic power devices are fabricated to completion on the wafer, the wafer is then physically sawed into separate individual sections commonly referred to as “die,” “microchips,” or “chips.” Each microchip corresponds to a particular device location on the previously unseparated wafer. Each microchip contains a separate microelectronic power device.
Instead of bonding and/or mounting an individual microchip within a separate package having external leads so that the microchip as packaged can be plugged and thereafter soldered into a circuit board via the leads, a microchip which contains a microelectronic power device is often directly soldered, in an unpackaged form, to a conductor pad previously formed on a substrate material or a printed circuit board. The unpackaged microchip is soldered such that the underside metallization of the microchip is in electrical contact, via the solder, to the conductor pad previously formed on the substrate material or the printed circuit board. Typically, the underside metallization of the microchip coincides with one or more active terminals of the microelectronic power device contained on the microchip. In addition, one or more other active terminals of the microelectronic power device may be electrically connected to other conductive areas of the substrate material or printed circuit board via, for example, wires which are bonded between active terminals which are located on the topside of the microchip and select conductive areas on the substrate material or printed circuit board.
The general technology involved in the soldering of an unpackaged chip directly to a conductor pad previously formed on a substrate or printed circuit board is commonly referred to as “direct chip attach” technology or “DCA.” Depending upon a particular electronic system's overall design requirements, DCA technology is often the technology of choice when it comes to physically combining microchips with printed circuit boards, for DCA technology offers better electrical performance, better thermal energy control, lower weight, smaller size, and lower cost.
In the particular case of directly soldering a microchip containing a microelectronic power device to a conductor pad, it is important that the solder joint between the microchip and the conductor pad have as low an electrical impedance and as low a thermal impedance as possible. Given that such a microelectronic power device accommodates and controls such high levels of electric current and, therefore, generates high levels of thermal energy, it is important that the solder joint between the microchip and the conductor pad neither significantly impedes the passage of current nor significantly impedes the flow of thermal energy between the microchip and the conductor pad.
A problem often encountered when a microchip is directly soldered to a conductor pad is the introduction of gas bubbles or gas pockets, commonly referred to as “voids,” which form in the solder itself during the soldering process and which remain trapped in the solder once the solder hardens. Such voids are often the result of flux gases which are introduced into the solder during the solder reflow process. Such voids are highly undesirable in a solder joint through which high levels of current and/or thermal energy are to pass because they act as both electrical and thermal insulators and thereby increase both the electrical impedance and thermal impedance through the joint.
SUMMARY OF THE INVENTION
The present invention provides a multi-layer conductor pad which can be formed on a substrate or a printed circuit board and which reduces the occurrence of gas voids in solder when an electronic device is soldered to the conductor pad. In general, the conductor pad comprises a uniform and electrically conductive base layer having an exposed interface surface. Upon this interface surface, a patterned layer is formed which covers some but not all of the interface surface. The compositions of the layers are chosen such that one of the base layer and the patterned layer is substantially solder-non-wettable and the other is substantially solder-wettable. The pattern is designed to create pathways of non-wettable surface areas which extend to the edges of the pad such that when an electronic device is soldered onto the conductor pad, gases resulting from the soldering reflow process are substantially evacuated via the pathways. Once the solder hardens, the number of gas voids remaining in the solder is significantly reduced. As a result, both the electrical impedance and the thermal impedance through the hardened solder are greatly reduced.
According to different preferred embodiments of the present invention, the patterned layer can take various forms. For example, strips of non-wettable surface areas can be deposited upon the interface surface to form plural, parallel channels to opposite side edges of the pad. Alternatively, strips of non-wettable surface areas can be formed orthogonally so as to intersect each other, thus forming evacuation pathways to all edges of the pad. In another preferred embodiment, the pathways radiate outwardly from the center of the pad in a star pattern.
In a preferred aspect of the invention, the conductor pad includes a uniform and electrically conductive base layer having an interface surface. A patterned layer is formed on the interface surface. The base layer is substantially wettable and the patterned layer is both substantially non-wettable and electrically conductive. The base layer and the patterned layer cooperatively define strips of non-wettable surface areas which extend across the interface surface of the base layer. The base layer comprises palladium and silver, and the patterned layer comprises a high concentration of silver. Furthermore, the strips of non-wettable surface areas are defined such that they are substantially parallel and spaced apart upon the interface surface of the base layer.
Advantages, design considerations, and applications of the present invention will become apparent to those skilled in the art when the detailed description of the best mode contemplated for practicing the invention, as set forth hereinbelow, is read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5077632 (1991-12-01), Kumagai et al.
patent: 5410449 (1995-04-01), Brunner
patent: 5480835 (1996-01-01), Carney et al.
patent: 6034332 (2000-03-01), Moresco et al.
patent: 6087596 (2000-07-01), Liu
patent: 6241533 (2001-06-01), Matsumoto
patent: 6246587 (2001-06-01), Chen
Downey Joel Franklin
Isenberg John Karl
Delphi Technologies Inc.
Funke Jimmy L.
Hyeon Hae Moon
Sircus Brian
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