Tuners – Variable inductor tuned
Reexamination Certificate
1998-12-22
2001-10-30
Pascal, Robert (Department: 2817)
Tuners
Variable inductor tuned
C333S236000
Reexamination Certificate
active
06310527
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a multi-layer circuit board including a reactance element and a method of trimming a reactance element in a circuit board.
2. Description of the Prior Art
A multi-layer printed circuit board including inductance trimming patterns is known. Japanese patent application provisional publication No. 62-109418 discloses a chip type delay element including an inductance pattern formed on a surface of a dielectric substrate and comb electrodes, wherein the comb electrodes are subjected to a laser cut process to provide a desired delay time.
Japanese patent application provisional publication No. 7-297637 discloses a resonating circuit board including a microstrip conductor as inductance element and a plurality of stab conductors for controlling the line length of the microstrip conductor, a capacitive electrode patterns, and timing conductors for trimming the capacitance of the capacitive electrode patters.
SUMMARY OF THE INVENTION
The aim of the present invention is to provide a superior multi-layer circuit board including a reactance element and a superior method of trimming a reactance element in a circuit board.
According to the present invention there is provided a multi-layer circuit board including: first to third conductive layers, the first and third conductive layers being grounded; a first dielectric substrate sandwiched between the first and second conductive layers; a second dielectric layer sandwiched between the second and third conductive layers; and a trimming reactance circuit including first and second circuit patterns at the second conductive layer cooperatively providing either of a first reactance or a second reactance, the second circuit pattern being to be cut as required, the first reactance being provided when the second circuit pattern is not cut and the second reactance being provided when the second circuit pattern is cut.
In the multi-layer circuit board, the first to third conductive layers and the first and second dielectric layers are successively arranged.
The multi-layer circuit board may further include a third dielectric layer and a fourth conductive layer on the third dielectric layer and the third dielectric layer and the fourth dielectric layer are sandwiched between the first dielectric substrate and the second conductive layer, wherein the trimming reactance circuit includes a capacitive element which is provided at the second and fourth conductive layers.
In the multi-layer circuit board, the trimming reactance circuit may include a coil circuit pattern having a hole therein and a side portion between the hole and an adjacent side edge of the coil circuit pattern corresponding to the second circuit pattern. In this case, the coil circuit pattern may have a plurality of holes. Moreover, in this case, a plurality of the holes may have different sizes.
According to the present invention there is further provided a first method of trimming a reactance element including the steps of: providing a multi-layer circuit board including first to third conductive layers, the first and third conductive layers being to be grounded; a first dielectric substrate sandwiched between the first and second conductive layers; a second dielectric layer sandwiched between the second and third conductive layers; and the reactance element at the second conductive layer; and selectively cutting a portion of the reactance element with an energy beam to trim a reactance of the reactance element. In this case, the portion may be cut by making a hole with the energy beam from the side of the first conductive layer, such that a depth of the hole reaches to the reactance element but does not reach to the third conductive layer. Moreover, the portion may be cut at a plurality points at the portion. Moreover, the reactance element includes a circuit pattern having a thickness and is cut to provide an interval equal to or larger than the thickness.
According to the present invention there is further provided a second method of trimming a reactance element including a circuit pattern at one of conductive layers of a multi-layer circuit board, comprising the steps of; operating the circuit board apparatus; observing an operating condition of the circuit board apparatus; and selectively cutting a portion the circuit with an energy beam in accordance with the operating condition.
In this case, the step of cutting the second circuit pattern may be effected while the circuit board apparatus is being operated. Moreover, the circuit pattern has a thickness and is cut to provide an interval larger than the thickness.
According to the present invention there is further provided a third method of trimming a coil circuit provided at one of conductive layers of a multi-layer circuit board apparatus, the coil circuit including a circuit pattern having a plurality of holes therein along the circuit pattern, for providing an initial inductance, each of holes being arranged between first and second side portions provided between side edges of the circuit pattern, including the steps of: operating the multi-layer circuit board apparatus; observing an operation condition of the multi-layer circuit board apparatus; determining a trimming inductance in accordance with the operation condition; and selectively cutting the first side portion of at least one of a plurality of the holes in accordance with the trimming inductance.
In the third method, the step of cutting is performed with an energy beam applied to the first side portion of at least one of the plurality of the hole.
In the third method, the plurality of holes have the same size and the method further comprising the step of determining the number of the holes of which one of the first side portion is cut in accordance with the trimming inductance.
In the third method, the plurality of holes have different sizes and the method further includes the step of determining which one of the holes of which the first side portion is cut in accordance with the trimming inductance.
The third method may further include the step of providing ground layers sandwiching the circuit pattern with isolation.
According to the present invention there is further provided a fourth method of trimming a capacitive circuit provided at one of conductive layers of a multi-layer circuit board apparatus, the capacitive circuit including first and second comb circuit patterns of which teeth of the first and second comb circuit patterns are interlaced with each other with isolation for providing a capacitance, including the steps of: operating the circuit board apparatus; observing an operation condition of the multi-layer circuit circuit board apparatus; determining a trimming capacitance in accordance with the operation condition; and selectively cutting a portion of the teeth of the first comb circuit patterns in accordance with the trimming capacitance.
In the fourth method, the step of selectively cutting a portion of the teeth of the first comb circuit patterns is performed with an energy beam applied to the portion.
The fourth method may further include the step of providing ground layers sandwiching the circuit pattern with isolation.
REFERENCES:
patent: 4470096 (1984-09-01), Guertin
patent: 5548537 (1996-08-01), Taguchi
patent: 0209816 (1987-01-01), None
patent: 62-109418 (1987-05-01), None
patent: 03 0883111 (1991-04-01), None
patent: 7-297637 (1995-11-01), None
patent: 102411990 (1998-09-01), None
Gomi Sadahiro
Ito Masayuki
Kaneko Tamotsu
Sugawara Hiroshi
Connolly Bove Lodge & Hutz
Glenn Kimberly E
Matsushita Electric - Industrial Co., Ltd.
Pascal Robert
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