Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1998-12-15
2001-02-27
Gandhi, Jayprakash N. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C361S792000
Reexamination Certificate
active
06194668
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-layer circuit board for mounting an electronic element such as a semiconductor chip having connection electrodes arranged in the form of a lattice or a semiconductor device having external connection terminals arranged in an area array form.
2. Description of the Related Art
In modern semiconductor devices, the logic devices are becoming highly functional and highly integrated, feature more inputs and outputs, and are being mounted ever more densely. Therefore, products have been produced, to compensate for a lack of space for forming electrodes, by arranging electrodes like a lattice on the electrode-forming surface of a semiconductor chip.
FIG. 26
illustrates an example in which a semiconductor chip
4
is mounted on a circuit board
5
relying on an ordinary flip chip connection. The semiconductor chip
4
has electrodes
6
arranged on the peripheral edges thereof. Circuit patterns
7
are connected to every electrode
6
on a surface.
FIG. 27
illustrates the arrangement of lands
8
and circuit patterns
7
on a circuit board for mounting a semiconductor chip. In this example, the lands
8
are arranged in two sequences, the circuit patterns
7
connected to the lands
8
of the inner side are drawn running among the neighboring lands
8
on the outer side; i.e., the circuit pattern
7
is drawn from every land
8
on a surface.
When the electrodes are arranged in many sequences on the electrode-forming surface, however, it becomes no longer possible to take out the wiring from every land on the surface though it may vary depending upon the distance between the lands and the number of the lands.
In order to solve this problem, a method has been proposed according to which the circuit board for mounting a semiconductor chip is formed in many layers, and circuit patterns are suitably arranged on each of the circuit boards that are laminated to connect all electrodes of the semiconductor chip to the circuit patterns.
FIG. 28
illustrates an example where a semiconductor chip
4
, on which many electrodes
6
are arranged like a lattice, is mounted on a multi-layer circuit board. By using this multi-layer circuit board, it is possible to electrically connect all electrodes
6
arranged in the form of a lattice to the circuit patterns
7
,
7
a
in order to electrically connect the external connection terminals
9
to the electrodes
6
. In
FIG. 28
, reference numeral
7
a
denotes a circuit pattern of an inner layer, and reference numerals
5
a
to
5
d
denote first to fourth circuit boards.
When the semiconductor chip having electrodes arranged like a lattice is to be mounted on the circuit board, two or more circuit boards may be laminated one upon the other to form a multi-layer circuit board provided that the number of the electrodes is not very large. When the semiconductor chip has as many pins as, for example, 30×30 pins or 40×40 pins, however, six to ten circuit boards must be laminated one upon the other.
When the circuit boards on which the circuit patterns are very densely formed are to be laminated in many layers, there will be employed a high-density wiring method such as build-up method accompanied, however, by serious problems in regard to yield of the products, reliability and the cost of production. That is, when many circuit patterns are to be laminated one upon the other, vias are formed in each board to accomplish an electric connection between the circuit patterns and the circuit patterns across the board, and the boards are successively laminated, requiring a high degree of precision without at present, however, offering a high degree of reliability. When many boards are laminated, furthermore, it is required that none of the boards is defective, involving further increased technical difficulty.
To produce a multi-layer circuit board maintaining a good yield, therefore, a reduction in the number of wiring layers could be an effective solution.
The present invention is concerned with a multi-layer circuit board for mounting an electronic part such as a semiconductor chip having as many as 40×40 pins in the form of a lattice on the side of the mounting surface, or a semiconductor device having electrodes arranged in the form of a lattice on the side of the mounting surface.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a multi-layer circuit board for mounting a semiconductor chip or a semiconductor device, with a reduced number of the circuit boards and, hence, an enhanced production yield of the multi-layer circuit boards, and offering high reliability.
In order to accomplish the above-mentioned object, the present invention is constituted as described below.
That is, the present invention is concerned with a multi-layer circuit board formed by laminating a plurality of circuit boards each having a large number of lands arranged in the form of a lattice or in a staggered manner on the side of the mounting surface and having circuit patterns with the ends on one side thereof being connected to said lands and with the ends on the other side thereof being drawn toward the outside from a region where said lands are arranged; wherein the lands for drawing the circuit patterns in a number of not smaller than a+1 are arranged on the oblique lines of an isosceles triangle having a base formed by consecutive lands of a number of n and having oblique lines in the diagonal directions, the value n satisfying m≧k+1 of the two values of:
m={(land pitch)×(n−1)−(land diameter)−(space between patterns)}÷(pattern width+space between patterns),
k=a(n−1)+(n−2),
wherein a is the number of the circuit patterns that can be arranged between the neighboring lands on the circuit board, and n is a parameter.
When n is an even number, furthermore, the lands for drawing the circuit patterns are arranged on a figure approximate to an isosceles triangle having the lands of the number of ((n/2)+1) arranged on one oblique line thereof.
Furthermore, the circuit patterns are drawn in a number of k+(n−1) or m for the value n.
The present invention relates to a multi-layer circuit board obtained by laminating plural pieces of circuit boards to mount an electronic part such as a semiconductor chip or a semiconductor device having many electrodes, and its object is to constitute a multi-layer circuit board by laminating a decreased number of the circuit boards (wiring layers) by contriving the arrangement of circuit patterns on each circuit board. There is no particular limitation on the method of forming the circuit board in many layers, and any method can be employed such as the build-up method.
The electrodes of an electronic part are usually arranged in the form of a normal lattice or in a staggered manner. Here, what is important is how the circuit patterns be arranged (drawn) in order to efficiently draw the circuit patterns with a least number of the circuit boards in a state where the electrodes are arranged in the form of a normal lattice or in a staggered manner.
The circuit patterns must be drawn to pass among the lands. In practically designing the circuit patterns, therefore, the circuit patterns must be drawn depending upon various conditions such as a pitch between the lands, diameter of the land, width of the pattern, distance between the patterns, etc.
The multi-layer circuit board of the present invention is related to a method of designing the circuit patterns on each circuit board constituting the multi-layer circuit board. The circuit patterns can be efficiently designed on the below-mentioned basis.
In designing the circuit patterns, first, consideration is given to a normal lattice arrangement in which the lands are arranged in the longitudinal and transverse directions maintaining an equal distance.
When the lands are arranged in a number of n maintaining an equal distance, and when the intermediate lands of the number of
Horiuchi Michio
Takeuchi Yukiharu
Yoda Eiji
Gandhi Jayprakash N.
Norris Jeremy
Pennie & Edmonds LLP
Shinko Electric Industries Co. Ltd.
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