Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2007-06-08
2011-11-29
Norris, Jeremy (Department: 2835)
Metal working
Method of mechanical manufacture
Electrical device making
Reexamination Certificate
active
08065795
ABSTRACT:
Processes for fabricating a multi-layer circuit assembly and a multi-layer circuit assembly fabricated by such processes are provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias, these area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a layer of metal to all surfaces of the substrate. Additional processing steps such as circuitization may be included.
REFERENCES:
patent: 3451793 (1969-06-01), Matsushita
patent: 3469982 (1969-09-01), Celeste
patent: 3738835 (1973-06-01), Bakos
patent: 3934334 (1976-01-01), Hanni
patent: 4137211 (1979-01-01), Angelo et al.
patent: 4343885 (1982-08-01), Reardon, Jr.
patent: 4378264 (1983-03-01), Pilette et al.
patent: 4592816 (1986-06-01), Emmons et al.
patent: 5153986 (1992-10-01), Brauer et al.
patent: 5224265 (1993-07-01), Dux et al.
patent: 5229550 (1993-07-01), Bindra et al.
patent: 5232548 (1993-08-01), Ehrenberg et al.
patent: 5242780 (1993-09-01), Lin et al.
patent: 5291066 (1994-03-01), Neugebauer et al.
patent: 5298685 (1994-03-01), Bindra et al.
patent: 5316787 (1994-05-01), Frankeny et al.
patent: 5319158 (1994-06-01), Lee et al.
patent: 5435057 (1995-07-01), Bindra et al.
patent: 5590460 (1997-01-01), DiStefano et al.
patent: 5600035 (1997-02-01), Kahle et al.
patent: 5879808 (1999-03-01), Wary et al.
patent: 5903428 (1999-05-01), Grimard et al.
patent: 6030693 (2000-02-01), Boyko et al.
patent: 6150284 (2000-11-01), Kawahara
patent: 6266874 (2001-07-01), DiStefano et al.
patent: 0 523 479 (1993-01-01), None
patent: 98/20559 (1998-05-01), None
patent: 02/073685 (2002-09-01), None
“Parylene Specifications and Properties”, Speedline Technologies, Product Literature, 2000.
Beach, W. F., “Xylylene Polymers”, Kirk-Othmer Encylopedia of Chemical Technology, Supplement Volume, 1998, pp. 863-901, John Wiley & Sons, New York, New York 10158-0012, United States of America.
Olson Kevin C.
Wang Alan G.
Lenart Robert P.
Norris Jeremy
PPG Industries Ohio, Inc
LandOfFree
Multi-layer circuit assembly and process for preparing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-layer circuit assembly and process for preparing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-layer circuit assembly and process for preparing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4294780