Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity
Reexamination Certificate
1998-03-17
2001-10-16
Pham, Long (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Tunneling through region of reduced conductivity
C257S351000
Reexamination Certificate
active
06303942
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to microelectronic devices, and particularly to devices that may serve as tunneling devices and systems, such as tunneling diodes, and extends to electrically erasable and programmable read only memory (abbreviated as “EEPROM”).
2. Description of the Related Art
The continual demand for enhanced transistor and integrated circuit performance has resulted in improvements in existing devices, such as silicon bipolar and complementary metal-oxide-silicon (CMOS) transistors and gallium arsenide metal-semiconductor field effect transistors (MESFETs), and also in the introduction of new device types and materials. In particular, scaling down device sizes to enhance high frequency performance leads to observable quantum mechanical effects such as carrier tunneling through potential barriers. This has led to development of alternative device structures such as resonant tunneling diodes and resonant tunneling hot electron transistors that take advantage of such tunneling phenomena.
More specifically, thin tunnel dielectric floating gate memory devices are also known in the art. In such devices, charge carriers are transported into and out of the floating metal or silicon gates through a relatively thin portion of a single layer of oxide (~10 nm) located between the floating gate and the device substrate. Transport mechanisms include Fowler-Nordheim (FN) tunneling through a triangular potential barrier or avalanche injection over the barrier. Thus in both cases, writing and erasing involve injection of charge into the conduction band of the oxide. Band diagrams illustrating the avalanche injection and FN processes are shown in
FIGS. 1 and 2
, respectively. [Betty Prince,
Semiconductor Memories, A Handbook of Design, Manufacture, and Application
, 2
nd
ed. (John Wiley and Sons, New York, N.Y., 1996) p. 183] Nonvolatility is possible because there exists a large bias region (at least several volts) between the write and erase bias levels where charge is not readily transported across the oxide by these mechanisms. This is illustrated by the current-voltage diagram of a known FN tunnel diode shown in FIG.
3
. Examples of thin tunnel dielectric floating gate memory devices are given in U.S. Pat. No. 4,019,197 to Lohstroh et al., U.S. Pat. No. 4,115,194 to Harari, and U.S. Pat. No. 4,203,158 to Frohman-Benchkowsky.
The FN and avalanche injection processes are known to degrade the oxide with the result that conventional devices can be cycled only a limited number of times (~10
3
-~10
6
) before the oxide fails. Once the oxide fails even locally, the whole floating gate is shorted to the substrate and charge storage is impossible. One attempt to remedy the problem has been to replace the floating gate metal or silicon with an insulating silicon nitride material, enabling the capture and emission of charge at localized trap sites related to the presence of the nitride. An example of such a device is given in U.S. Pat. No. 4,112,507 to White et al. In this type of system, oxide failure at one trap site does not lead to total device failure. These devices can endure up to ~10
8
write/erase cycles. Other silicon-based approaches to nonvolatile storage, such as “flash” technology can also lead to as much as ~10
8
write/erase cycles, but all of these approaches are still limited by the reliability of the dielectric under the stress of writing and erasing by FN tunneling or avalanche injection.
A modified approach to charge storage involves using a single layer direct tunnel (DT) oxide to separate the floating gate from the substrate. Direct tunnel oxides are so thin that significant tunneling is possible across the whole thickness of the dielectric, through a trapezoidal potential barrier, without the need for injection into the oxide conduction band. Band diagrams and the resulting current voltage behavior for the direct tunneling mechanism of charge injection are shown in
FIGS. 4 and 5
, respectively. [P. V. Dressendorfer,
Interface and Electron Tunneling Properties of Thin Oxides on Silicon
, Ph.D. thesis, Yale University, 1978, pp. 141 and 149.] Significant nonvolatility has not been shown to be possible in conventional type devices with single layer DT oxides because, unlike for thicker FN or avalanche oxides, there is no bias region between the write and erase levels where substantial tunnel leakage does not occur. This is evident in the plot of FIG.
5
.
Nonetheless, using DT oxides would still be advantageous because of an effect discovered by the present applicant, that DT oxides do not seem to degrade if the voltage across them is kept within the range −3 V<V
gate
<+1 V. [K. R. Farmer, M. O. Andersson and O. Engstrom, “Tunnel Electron Induced Charge Generation in Very Thin Silicon Oxide Dielectrics,”
AppL. Phys. Lett
. 60, 730 (1992)] One memory device that attempts to exploit this advantage, proposed by researchers at IBM, is a quasi-nonvolatile device where charge storage is done on isolated nano-crystals of silicon, separated from the substrate by a direct tunnel oxide. [H. I. Hanafi, S. Tiwari and I. Khan, “Fast and Long Retention-Time Nano-Crystal Memory,”
IEEE Trans. Electron Devices
43, 1553 (1996); and S. Tiwari, “Silicon Nano-Crystal Memories: Devices in the Limit of Conventional Miniaturization,” in
The Physics and Chemistry of SiO
2
and the Si
-
SiO
2
Interface—3, H. Z. Massoud, E. H. Poindexter, and C. R. Helms, Editors, Proc. Vol. 96-1, p. 250, The Electrochemical Society, Pennington, N.J., 1996] The device shows that over 10
9
cycles are possible using direct tunnel oxides, but it is not truly nonvolatile because, even though a Coulomb blockade effect associated with the nano-crystals may be present to enhance charge retention, still the stored charge leaks off the nano-crystal sites over a period of hours.
FN or direct tunneling diodes are the heart of the previous memory constructions. A more complex diode that is also known in the art is the resonant tunneling diode (RTD) structure. These devices rely on resonant tunneling through a quantum well in a single band. RTDs are two terminal devices with conduction carriers tunneling through trapezoidal potential barriers to yield current-voltage curves with portions exhibiting negative differential resistance. A representative band diagram for an unbiased RTD is shown in FIG.
6
. The original Esaki diode had interband tunneling (e.g., from conduction band to valence band) in a heavily doped pn junction diode. In some materials systems, such as strained layer SiGe/Si heterostructures, the valence band offset greatly exceeds the conduction band offset at the interfaces, thus in these systems most investigators consider the tunneling of holes rather than electrons.
Mars et al., “Reproducible Growth and Application of AlAs/GaAs Double Barrier Resonant Tunneling Diodes,”
J. Vac. Sci. Tech. B
965 (1993); and Özbay et al., “110-GHz Monolithic Resonant-Tunneling-Diode Trigger Circuit,”
IEEE Elec. Dev. Lett.
480 (1991), each use two AlAs tunneling barriers imbedded in a GaAs structure to form a quantum well RTD. The quantum well may be 4.5 nm thick with 1.7 nm thick tunneling barriers.
FIG. 7
illustrates current-voltage behavior at room temperature. Note that such resonant tunneling diodes are symmetrical. With the bias shown in
FIG. 8
a
, a discrete electron level (bottom edge of a subband) in the quantum well aligns with the cathode conduction band edge, so resonant electron tunneling readily occurs, and the current is large. In contrast, with the bias shown in
FIG. 8
b
, the cathode conduction band aligns between quantum well levels and suppresses tunneling, and the current is small. For device applications, negative resistance is the distinguishing feature of the RTD's, and by itself would not necessarily be expected to improve the retention characteristics of nonvolatile memory because, as illustrated in
FIG. 7
, tunnel leakage might still be expected.
Ts
Coleman William David
Klauber & Jackson
Pham Long
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