Multi-input zero offset comparator

Details Multi-input zero offset comparator Multi-input zero offset comparator

1983-12-19

1986-05-20

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307357, 307360, 307364, H03K 524, G01R 19165

Patent

active

045903913

ABSTRACT:
A multiple input window comparator for use in apparatus requiring sensing of a voltage window, such as power supplies and system monitors, including a first comparator having multiple input transistors, each of which receives a signal to be compared. The comparator characteristics for each input signal are balanced through the use of a current mirror circuit connected to each input transistor. A complementary second comparator circuit is provided which, in combination with the first comparator circuit, produces a signal indicating when one or more of the input signals exceeds the voltage boundaries (voltage window) defined by reference signals of the first and second comparator. The circuit topology of each of the first and second comparators produces a zero input voltage offset with respect to the respective reference voltage, such that the comparator output signal occurs substantially instantaneously and uniformly with the transition of the threshold voltage by one or more of the input signals. The comparator may be implemented with separate, discrete components or entirely on a single integrated circuit.

REFERENCES:
patent: 3735151 (1973-05-01), Frederiksen et al.
patent: 4177394 (1979-12-01), Takasugi
patent: 4300063 (1981-11-01), Dunphy et al.

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