Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
1999-11-18
2002-05-14
Shingleton, Michael B (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S252000, C330S257000
Reexamination Certificate
active
06388519
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-input differential amplifier circuit having two or more pairs of positive and negative input terminals.
2. Description of the Related Art
In a differential amplifier circuit, particularly a multi-input type differential amplifier circuit having two or more pairs of positive and negative input terminals, use is made of a configuration in which an input dynamic range is broadened by connecting drains of transistors configuring a positive side input element to a common node, connecting drains of transistors configuring a negative side input element to another common node, and supplying an operating current by a different current source for every differential pair. A multi-input type differential amplifier circuit having such a configuration was disclosed in Japanese Unexamined Patent Publication (Kokai) No. 9-93052.
FIG. 49
is a circuit diagram of an example of the multi-input type differential amplifier circuit disclosed in Japanese Unexamined Patent Publication (Kokai) No. 9-93052. As illustrated, in this multi-input type differential amplifier circuit, n number of differential pairs are configured by MOS transistors MI
01
, . . . , MI
0n
and MI
11
, . . . , MI
1n
. The gates of the transistors MI
01
, . . . , MI
1n
configure the positive side input terminals, while the gates of the transistors MI
01
, . . . , MI
0n
configure the negative side input terminals. The drains of the positive side transistors are connected to a common negative node ND
N
, while the drains of the negative side transistors are connected to a common positive node ND
p
. The node ND
N
is connected to w a supply line of a power supply voltage V
DD
via a load resistor circuit RL
1
, while the node ND
P
is connected to the supply line of the power supply voltage V
DD
via a load resistor circuit RL
0
. The sources of the two transistors such as the transistors MI
01
and MI
11
, configuring each differential pair are connected to a common node, while operating currents are supplied to these nodes by different current sources. For example, the sources of the pair transistors MI
01
and MI
11
are connected to a node VS
1
, while the sources of the pair transistors MI
0n
n and MI
1n
are connected to a node VS
n
. An operating current ID
1
is supplied to the node VS
1
by a current source IS
1
, while an operating current ID
n
is supplied to the node VS
n
by a current source IS
n
.
FIG. 50
is a view of an example of the multi-input type differential amplifier circuit shown in FIG.
49
. Note that, here, a so-called 4-terminal input differential amplifier circuit having two positive and negative input terminals is shown.
As illustrated, in this differential amplifier circuit, an output load circuit is configured by a current mirror circuit configured by p-channel MOS transistors ML
0
and ML
1
. Namely, both of the sources of the transistors ML
0
and ML
1
are connected to the supply line of the power supply voltage V
DD
, the gates of these transistors are connected to each other, and a connection point thereof is connected to the drain of the transistor ML
0
. The drain of the transistor ML
0
is connected to the common node ND
p
of the drains of the positive side transistors MI
01
and M
02
, while the drain of the transistor ML
01
is connected to the common node ND
N
of the negative side transistors MI
11
and MI
12
.
Further, the current source for supplying the operating current to each differential pair is configured by n-channel MOS transistors MS
1
and MS
2
to the gate of which a predetermined bias voltage is applied. For example, the drain of the transistor MS
1
is connected to the node VS
1
, while the drain of the transistor MS
2
is connected to the node VS
2
. A bias voltage V
BIAS
is input to the gates of these transistors MS
1
and MS
2
. Note that the bias voltage V
BIAS
is created by the current source IS
0
and the nMOS transistor MS
0
.
The node ND, and the node ND
N
configure a non-inverted output terminal DFO(+) and an inverted output terminal DFO(−) of the differential amplifier circuit. The output signal of the inverted output terminal DFO(−) is input to a push-pull output stage configured by transistors PT
1
and NT
1
via a source follower configured by transistors ML
2
and MS
3
. The output signal of the source follower is amplified by the push-pull output stage and output to the output terminal OUT. Note that a resistance element R
1
and a capacitor C
1
forming a phase compensation circuit are connected in series between the inverted output terminal DFO(−) of the differential amplifier circuit and the output terminal OUT of the push-pull output stage.
FIG. 51
is a view of an example of another configuration of the multi-input type differential amplifier circuit. As illustrated, the differential amplifier circuit of the present example is a 6-terminal input differential amplifier circuit configured by three differential pairs. The configuration of the circuit of the example is substantially the same as the 4-terminal input differential amplifier circuit shown in
FIG. 50
except that it has three differential pairs. Note that in this circuit, the current amplification rates of the transistors configuring the differential pairs are set to different values, therefore an amplification signal weighted with respect to the input signal is obtained.
When the current amplification rate of transistors MI
01
and MI
11
is &bgr;
1
, the current amplification rate of the transistors MI
02
and MI
12
is &bgr;
2
, the current amplification rate of transistors MI
03
and MI
13
is &bgr;
3
, and the ratio of the current amplification rates of the transistors MS
1
, MS
2
, and MS
3
is &bgr;
1
:&bgr;
2
:&bgr;
3
, the differential signal input to each differential pair is weighted in accordance with the current amplification rate of the transistors configuring each differential pair, thus the amplification signal is obtained.
In the multi-input type differential amplifier circuit mentioned above, when the differential amplifier circuit is used by supplying a negative feedback between the input and the output, the usual differential amplifier circuit having only one pair of positive and negative input terminals operates based on a state where the voltage of the positive side input terminal and the voltage of the negative side input terminal are equal (virtual ground), but in contrast, in a multi-input type differential amplifier circuit, the voltage of the positive side input terminal and the voltage of the negative side input terminal do not have to be equal for every pair, so it operates based on a state where the summation of voltages of the positive side input terminals and the summation of voltages of the negative side input terminals become equal.
Namely, a multi-input type differential amplifier circuit must operate even in a case where voltages of the positive side input terminal and the negative side input terminal are different for every differential pair. When looking at the drain voltage of the transistor configuring a current source for supplying an operating current to a differential input pair, however, this becomes the output voltage of an OR type source follower circuit using positive and negative input terminals as two input terminals. For this reason, when there is a difference between the voltages of the positive and negative input terminals of more than the threshold voltage of the transistors configuring an input element, the output voltage of the OR type source follower circuit becomes a voltage shifted from the gate voltage of the transistor which is further turned on between the two transistors configuring the input element by the value of the threshold voltage V
th
, so a voltage required for turning on the related transistor will not be supplied between the gate and the source of the transistor configuring the other input element.
As a result, when the voltages of the positive and negative input terminals are separated from each oth
Kananen, Esq. Ronald P.
Rader & Fishman & Grauer, PLLC
Shingleton Michael B
Sony Corporation
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