Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2005-02-15
2005-02-15
Mai, Son (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S051000, C365S063000
Reexamination Certificate
active
06856572
ABSTRACT:
A memory array decoder organization readily interfaces to array lines having extremely dense pitch, and in particular interfaces to extremely dense array lines of a three-dimensional memory array. In an exemplary embodiment, a multi-headed decoder includes a group of array line driver circuits associated with a single decode node. Each array line driver circuit couples its associated array line through a first device to an associated upper bias node which is generated to convey either a selected bias condition or an unselected bias condition thereon appropriate for the array line. Each array line driver circuit also couples its associated array line through a second device to an associated lower bias node which is generated to convey an unselected bias condition appropriate for the array line. The array line driver circuits for several different decode nodes may be physically arranged in one or more banks.
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Crowley Matthew P.
Scheuerlein Roy E.
Mai Son
Matrix Semiconductor Inc.
Zagorin O'Brien Graham LLP
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