Multi-GB/S data pulse receiver

Details Multi-GB/S data pulse receiver Multi-GB/S data pulse receiver

1998-04-03

2000-05-02

Bocure, Tesfaldet

Pulse or digital communications

Receivers

H04L 2706

Patent

active

060581441

ABSTRACT:
A data pulse receiver for detecting and amplifying substantially attenuated data pulses received at gigabit-per-second rates from a differential coupler with outputs having asymmetrical dc characteristics. The receiver, in a preferred embodiment, has grounded base differential amplifiers to give impedance matching, a biasing resistor connected to a separate ground terminal for biasing one of the differential amplifiers, and a matching resistor, connected at only one of its terminals, to compensate for the stray capacitance of the biasing resistor. A regenerative flip-flop with programmable tail current provides hysteresis in order to suppress unwanted noise. The receiver may also include means for automatic adjustment of the hysteresis level.

REFERENCES:
patent: 4430580 (1984-02-01), Lovelace
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patent: 4742309 (1988-05-01), Chu
patent: 5432486 (1995-07-01), Wong
patent: 5852637 (1998-12-01), Brown et al.
"Bus-Driver ICs", Quinnell, R.A., et al, Electrical Design News (EDN), 37, No. 3, Feb. 3, 1992, pp. 78-86.
Gray & Meyer, "Analysis and Design of Analog Integrated Circuits", Wiley, 3.sup.rd Edition 1993, p. 497.

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