Multi function patch pin circuit

Details Multi function patch pin circuit Multi function patch pin circuit

1977-11-23

1981-02-10

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307254, 307361, H03K 10082, H03K 1762, H03K 5153

Patent

active

042504074

ABSTRACT:
A single patch on an integrated circuit is arranged to patch any one of four different logical states into the circuit, according to whether the pin is grounded, floating, coupled to a supply rail via a resistor, or coupled to the supply rail directly. In one embodiment, the voltage thresholds of three transistors are arranged so that they switch on successively in response to successively higher voltages on the patch pin, thereby controlling the binary logic signals at each of two output points in the circuit; in the other embodiment, multi-emitter transistors are arranged with differing current thresholds to achieve the same result.

REFERENCES:
patent: 3155845 (1964-11-01), Gruddis et al.
patent: 3207922 (1965-09-01), Gruddis et al.
patent: 3609411 (1971-09-01), Ma et al.
patent: 3660677 (1972-05-01), Maley et al.
patent: 3660678 (1972-05-01), Maley et al.
patent: 3671763 (1972-06-01), Maley et al.
patent: 3969633 (1976-07-01), Paluck et al.
Lindgren et al., "Three-State Receiver Logical Circuit", IBM Tech. Discl. Bull., vol. 19, No. 2, pp. 661-662, 7/1976.
Miller, "A Non-Synchronous Computer Circuit", RCA Technical Notes, TN No. 562, 3 sheets, 3/1964.

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