Multi-finger current ballasting ESD protection circuit and...

Details Multi-finger current ballasting ESD protection circuit and... Multi-finger current ballasting ESD protection circuit and...

2001-06-14

2003-06-24

Nguyen, Matthew (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

06583972

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to electrostatic discharge (ESD) protection, and, more particularly, to ESD protection circuits for reducing the voltage stress on integrated circuits during an ESD event.
Various types of circuits and other devices are vulnerable to damage from electrostatic discharge (ESD). ESD occurs when, for example, a user becomes electrostatically charged, for example by friction or induction and then discharges through a pin of the integrated circuit. Integrated circuits (ICs), particularly ICs formed of MOS (metal-oxide semiconductor) transistors, are especially vulnerable to such ESD damage. ESD may be inadvertently applied to input/output (I/O) or power pins or other pads of the IC, which can damage sensitive semiconductor junctions, dielectrics, interconnections or other sub-elements of the IC.
Various protection techniques have been developed to protect circuitry from ESD. The main goal of ESD protection is to shunt ESD-caused current away from vulnerable circuitry and through a special circuit path designed to handle such events at low voltages. Thus, the high voltage and current caused by an ESD event is diverted away from the main circuitry of the integrated circuit (IC). Such ESD circuits or structures (sometimes referred to as ESD protection circuits or clamps) may, for example, be placed in parallel across two input pins or pads, such as an I/O pad and ground, and therefore also in parallel across sensitive circuitry coupled to the two pads. Ideally, such ESD protection is unobtrusive or “invisible” to the normal operation of the circuit, so that its presence does not slow down or otherwise negatively impact the operation of the remaining IC circuitry when no ESD event is occurring.
Two commonly-used ESD protection structures are the SCR (silicon or semiconductor controlled rectifiers), and the npn bipolar transistor. Both types of structures exhibit a low-voltage, low-resistance state (known as the holding or clamping voltage) when a certain triggering voltage (or current) has been reached. Usually, the triggering voltage is higher than the holding voltage. Unless specifically designed otherwise, the SCR usually has the lowest holding voltage.
SCRs have been used, both parasitically and deliberately, to protect ICs, such as the SCR techniques described in U.S. Pat. Nos. 4,400,711, 4,405,933, 4,631,567 and 4,692,781. The major advantage of these SCR protection structures is their high energy-absorbing capability. Similarly, various forms of protection structures have been built around the npn snap-back phenomenon, such as the structures and techniques described in U.S. Pat. No. 5,519,242. This and similar structures take advantage of the parasitic npn bipolar junction transistor (BJT) existing in every NMOS transistor. Many of these approaches are now known as variants of the grounded-gate NMOS (ggNMOS).
Various problems have accompanied conventional ESD protection techniques. For example, large ESD protection device widths may be used to protect against large ESD events. In integrated circuit design, large device widths are achieved by using a multi-finger layout. A major concern with regard to multi-finger devices under ESD stress is the possibility of non-uniform triggering of the fingers. Curves
102
and
103
of
FIG. 1
illustrate the behavior of a single parasitic BJT. When the voltage across the BJT exceeds V
t1
, the BJT operates in a snapback mode to conduct current, thus, reducing the voltage across the protected circuitry. As shown by the curves
102
and
103
in
FIG. 1
, in order to ensure uniform turn-on of multi-finger structures, the voltage value at failure, V
t2
, must exceed the triggering voltage V
t1
of the parasitic BJT transistor, i.e. the voltage at the onset of snapback. This ensures that a second parallel finger will trigger at around V
t1
, before the first conducting finger reaches V
t2
. Thus, damage to an initially triggered and first conducting finger can be avoided until adjacent fingers are also switched on into the low resistive ESD conduction state (i.e. snapback). To achieve the condition V
t1
<V
t2
either the triggering voltage must be reduced or the second breakdown voltage must be increased.
Common methods to achieve the uniform conduction condition V
t1
<V
t2
in NMOS transistors are gate coupling and substrate triggering, as shown by the curves
104
and
105
of FIG.
1
. Gate coupling is described in an article by C. Duvvury et al. entitled “Dynamic Gate Coupling of NMOS for Efficient Output ESD Protection,” IRPS 1992 (IEEE catalog number 92CH3084-1) pp. 141-150. These techniques typically employ a capacitor coupled between the drain and the gate of the MOS transistor. A portion of the current resulting from an ESD event is transmitted through the capacitor to transiently bias the parasitic bipolar junction transistor (BJT) which is inherent to the MOS device.
By transiently biasing the NMOS gate and/or the base of the BJT during an ESD event, the ESD trigger voltage V
t1
decreases to V
t1
′, toward the snapback holding voltage V
h
intrinsically situated below V
t2
. The transient biasing is designed to be present for a time interval sufficient to cause all parallel fingers to fully conduct the ESD current. The gate coupling and/or substrate triggering generally change the NMOS high current characteristic from the curves
102
and
103
to the curves
104
and
103
. Moreover, these techniques also make it possible for NMOS transistors with a characteristic represented by curves
102
and
105
, which may be inappropriate for ESD protection, to be modified to have a more appropriate characteristic represented by curves
104
and
105
.
A general drawback of these methods, in particular with regard to radio frequency (RF) applications is the relatively large additional capacitance which is introduced at the I/O pads. Another drawback is the design complexity of the dynamic biasing circuitry which is typically designed to handle ESD events having many different time signatures.
One method for increasing V
t2
is to add ballasting resistance, e.g. by an increase of the drain contact to gate spacing in conjunction with silicide blocking as shown in FIG.
4
A. However, the additional process steps for the local silicide blocking in semiconductor manufacturing are costly and known for yield losses. The fully silicided multi-finger NMOS device (
FIGS. 4B and 4D
) is susceptible to ESD currents because no ballasting resistance is available. The introduction of fully silicided regions (
FIG. 4C
) in the drain and source region leads to very large device dimensions without evidence of actual improvement of the ESD device performance. Again, additional capacitance is added in form of junction capacitance by the increased drain area.
A general drawback of adding ballast resistance is the increased holding voltage under high current conduction. This leads to a higher power dissipation and thus inherently to a lower ESD performance. This also leads to a higher voltage build-up across the protection device and, thus, across the protected circuit node. Another general drawback of adding ballast resistance is the reduction of NMOS drive current and speed for normal operating conditions.
It is therefore desirable for an ESD protection circuit or clamp to have a known multi-finger performance without using dynamic biasing and in implementations that do not add either additional capacitance or additional ballast resistance. Furthermore, it is desirable to have an ESD performance that varies as a linear function of the structure width.
SUMMARY OF THE INVENTION
The present invention is embodied in a multi-finger ESD protection circuit having at least two first resistive channels defining input fingers. First and second field effect transistors (FETs) each having drain, source and gate terminals are includes. Each of the first and second FETs defines a respective parasitic bipolar junction transistor (BJT) between the first and second circuit terminals. The base of the BJT corre

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