Multi-emitter transistor having heavily doped N+ regions surroun

Details Multi-emitter transistor having heavily doped N+ regions surroun Multi-emitter transistor having heavily doped N+ regions surroun

1974-05-14

1976-03-23

Larkins, William D.

357 36, 357 48, 357 63, 357 89, H01L 2704, H01L 29167

Patent

active

039464253

ABSTRACT:
In a semiconductor integrated circuit device in which a plurality of regions each having a semiconductor element such as a PN junction diode and a transistor are isolated electrically from one another by PN junctions formed between the respective regions and a semiconductor isolation region, gold is introduced into the regions having the semiconductor elements and the isolation region while at least one diffused region heavily doped, for example, with phosphorus is formed in the isolation region adjacent to the region having the PN junction diode or the transistor thereby to prevent the breakdown voltage of the backwardly biased PN junction in the diode or the transistor from decreasing. Further by surrounding all the transistors, at least in one of which gold is diffused, formed in one integrated circuit with heavily doped N.sup.+-type regions an integrated circuit with transistors having a small variation in current amplification factor is obtained.

REFERENCES:
patent: 3312882 (1967-04-01), Pollock
patent: 3430110 (1969-02-01), Goshgarian
patent: 3486950 (1969-12-01), Lesk
patent: 3602779 (1971-08-01), Chapron
patent: 3607468 (1971-09-01), Chang et al.
patent: 3702955 (1972-11-01), Kalb et al.
patent: 3899793 (1975-08-01), Wakamiya et al.

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