Multi-element circuit construction

Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

361395, 361413, H05K 114

Patent

active

045743312

ABSTRACT:
A packaging construction for electronic circuit package elements, such as printed circuit boards and integrated-circuit chip packages, to obviate the need for connector cables, back-panel wiring and similar techniques. Circuit packaging elements are interconnected through an interconnection medium that includes an insulated board with opening through it, and a number of connector elements in the form of compressible wads of conductive wire. The connector elements are disposed in selected openings in the insulated board and compressed into contact with contact areas formed on the circuit package elements. Shorter lead lengths and improved circuit operating speed are the principal results of the approach. In a three-dimensional construction employing the principles of the invention, chip packages are arranged in modules, and interconnections may be made between chip packages within each module, transversely between modules, and in a third direction between layers of modules. The construction provides direct interconnections without the use of solder, connector cables or multilayer circuit boards, and makes most effective use of high-speed integrated circuitry.

REFERENCES:
patent: 482372 (0000-01-01), Smolley
patent: 1961578 (1934-06-01), Bowers
patent: 2853656 (1958-09-01), Dowds
patent: 2872664 (1959-02-01), Minot
patent: 2889532 (1959-06-01), Slack
patent: 3077511 (1963-02-01), Bohrer et al.
patent: 3148310 (1964-09-01), Feldmen
patent: 3264525 (1966-08-01), Swengel et al.
patent: 3281751 (1966-10-01), Blair
patent: 3312878 (1967-04-01), Poch et al.
patent: 3327278 (1894-06-01), Godel
patent: 3354260 (1967-11-01), Brandt et al.
patent: 3452149 (1969-06-01), Rinaldi
patent: 3487541 (1970-01-01), Doswell
patent: 3509270 (1970-04-01), Dube et al.
patent: 3541222 (1970-11-01), Parks et al.
patent: 3569607 (1971-03-01), Martyak
patent: 3605063 (1971-09-01), Stewart
patent: 3616532 (1971-11-01), Beck
patent: 3621564 (1971-11-01), Tanaka et al.
patent: 3639978 (1972-02-01), Schurmaan
patent: 3680037 (1972-07-01), Nellis et al.
patent: 3701964 (1972-10-01), Cronin
patent: 3795047 (1974-03-01), Abolafia et al.
patent: 3885173 (1975-05-01), Lee
patent: 3971610 (1976-07-01), Buchoff et al.
patent: 4029375 (1977-06-01), Garielian
patent: 4074342 (1978-02-01), Honn et al.
patent: 4164003 (1979-08-01), Cutchaw
patent: 4184729 (1980-01-01), Parks et al.
patent: 4249302 (1981-02-01), Crepeau
patent: 4363076 (1982-12-01), McIver
Microminiaturization-Electronics, pp. 92-94, 11-25-1960.
Three-Dimensional Packaging Method Permits Quick Servicing-Electronic Design, 3-16-1960, pp. 126-132.
Stacked, Sealed used in Sylvania Electronic Design, Jun. 22-1960, pp. 28 and 29.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Multi-element circuit construction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-element circuit construction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-element circuit construction will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1596658

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.